From patchwork Thu Feb 18 13:46:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 8349741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0D17D9F372 for ; Thu, 18 Feb 2016 13:48:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1B6C220395 for ; Thu, 18 Feb 2016 13:48:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0ACD32038D for ; Thu, 18 Feb 2016 13:48:23 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aWOux-0004kD-KI; Thu, 18 Feb 2016 13:46:51 +0000 Received: from mail-lb0-x22e.google.com ([2a00:1450:4010:c04::22e]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aWOus-0004Xh-7Q for linux-arm-kernel@lists.infradead.org; Thu, 18 Feb 2016 13:46:48 +0000 Received: by mail-lb0-x22e.google.com with SMTP id of3so28603134lbc.1 for ; Thu, 18 Feb 2016 05:46:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=CX7+YWDuEApWzjjISQ2hBDQlsg/GnesdcXq0RAUr9Vs=; b=WZaxtlTOTr4rsbOyeWT8xftMg5nDyPrHe3/p01cSB+FrdOUpn5HVR62BqMr1sDkalL lLL0DRtcReqRdy6wHcnP0u+VQof8LBFCzCZ4WPpY/xcwkQKI0KbYcbUJZEOxHG8VwfSb HXyEymUXKDXj1U4/c3B/by5CYx2CR9IITiDSQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=CX7+YWDuEApWzjjISQ2hBDQlsg/GnesdcXq0RAUr9Vs=; b=myQKb/RVh9FOWaASAlGEXLHhxsA/uo87wbly6z2ThPfUqn+SxwkzY4KD7btiQLpAgt cm9YORBFKVf0jUXIHrWnkjRdQbZhKQLnPk38EHMppkOzJXNgra4T/joJ+P3eYSIt/i47 uD3ww6KkDD865LY3LcO2ZYvhNqlOwTW4rKXk2iUHKvER6FuK8UkGcXzhtt4t1U52jsyG AkgyItrZCqsStCYDMMEWMVphOfIZn1BYpwg9Y2G7LNEop0Oe5qQvIKw+awRcE03tvl7p 8/YSxiqLfVe2KiNdF6ov5spNZyHOSho5a+e32Ofyszo2nWKf51opIHImMPugk4AAF11W eLkg== X-Gm-Message-State: AG10YOS0uWGoLg2hw17uPsIIvevD74JU3gv93GHZUWOi6mq1ZhUnTNEZX4GS/Sgy8NTms+oE X-Received: by 10.112.125.9 with SMTP id mm9mr2659836lbb.113.1455803183831; Thu, 18 Feb 2016 05:46:23 -0800 (PST) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id ke9sm950672lbc.28.2016.02.18.05.46.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Feb 2016 05:46:23 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Marc Zyngier Subject: [PATCH 1/3] irqchip: gic/realview: support more RealView DCC variants Date: Thu, 18 Feb 2016 14:46:12 +0100 Message-Id: <1455803172-22747-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160218_054646_657865_91696CE3 X-CRM114-Status: GOOD ( 21.21 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Russell King , Pawel Moll , devicetree@vger.kernel.org, Linus Walleij , Will Deacon MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In the add-on file for the GIC dealing with the RealView family we currently only handle the PB11MPCore, let's extend this to manage the RealView EB ARM11MPCore as well. The Revision B of the ARM11MPCore core tile is a bit special and needs special handling as it moves a system control register around at random. Cc: Arnd Bergmann Cc: Marc Zyngier Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Rob Herring --- This can be applied in isolation from the other patches so Marc one you're happy with it, please take it into the IRQchip tree. There are two compatible strings getting added to the device tree bindings so CC to the DT list. No biggie though, just figures out exactly what ARM custom GIC flavor it is. --- .../bindings/interrupt-controller/arm,gic.txt | 2 ++ drivers/irqchip/irq-gic-realview.c | 35 ++++++++++++++++++---- 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt index 5a1cb4bc3dfe..0c80e6870645 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt @@ -16,6 +16,8 @@ Main node required properties: "arm,cortex-a15-gic" "arm,cortex-a7-gic" "arm,cortex-a9-gic" + "arm,eb11mp-gic" + "arm,eb11mp-revb-gic" "arm,gic-400" "arm,pl390" "arm,tc11mp-gic" diff --git a/drivers/irqchip/irq-gic-realview.c b/drivers/irqchip/irq-gic-realview.c index aa46eb280a7f..224e83d5c056 100644 --- a/drivers/irqchip/irq-gic-realview.c +++ b/drivers/irqchip/irq-gic-realview.c @@ -10,7 +10,8 @@ #include #define REALVIEW_SYS_LOCK_OFFSET 0x20 -#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 +#define REALVIEW_SYS_PLD_CTRL1 0x74 +#define REALVIEW_EB_REVB_SYS_PLD_CTRL1 0xD8 #define VERSATILE_LOCK_VAL 0xA05F #define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24) #define PLD_INTMODE_LEGACY 0x0 @@ -18,26 +19,50 @@ #define PLD_INTMODE_NEW_NO_DCC BIT(23) #define PLD_INTMODE_FIQ_ENABLE BIT(24) +static const struct of_device_id syscon_pldset_of_match[] = { + { + .compatible = "arm,realview-eb-syscon", + }, + { + .compatible = "arm,realview-pb11mp-syscon", + }, + {}, +}; + static int __init realview_gic_of_init(struct device_node *node, struct device_node *parent) { static struct regmap *map; + struct device_node *np; + struct pld_setting *pldset; + u32 pld1_ctrl = REALVIEW_SYS_PLD_CTRL1; + + np = of_find_matching_node_and_match(NULL, syscon_pldset_of_match, + (void *)&pldset); + if (!np) + return -ENODEV; + + /* For some reason RealView EB Rev B moved this register */ + if (of_device_is_compatible(np, "arm,eb11mp-revb-gic")) + pld1_ctrl = REALVIEW_EB_REVB_SYS_PLD_CTRL1; /* The PB11MPCore GIC needs to be configured in the syscon */ - map = syscon_regmap_lookup_by_compatible("arm,realview-pb11mp-syscon"); + map = syscon_node_to_regmap(np); if (!IS_ERR(map)) { /* new irq mode with no DCC */ regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, VERSATILE_LOCK_VAL); - regmap_update_bits(map, REALVIEW_PB11MP_SYS_PLD_CTRL1, + regmap_update_bits(map, pld1_ctrl, PLD_INTMODE_NEW_NO_DCC, PLD_INTMODE_MASK); regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000); - pr_info("TC11MP GIC: set up interrupt controller to NEW mode, no DCC\n"); + pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n"); } else { - pr_err("TC11MP GIC setup: could not find syscon\n"); + pr_err("RealView GIC setup: could not find syscon\n"); return -ENXIO; } return gic_of_init(node, parent); } IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init); +IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init); +IRQCHIP_DECLARE(armeb11mp_revb_gic, "arm,eb11mp-revb-gic", realview_gic_of_init);