From patchwork Fri Feb 19 06:50:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dirk Behme X-Patchwork-Id: 8356811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BCE8FC0553 for ; Fri, 19 Feb 2016 06:52:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D9DCF2034F for ; Fri, 19 Feb 2016 06:52:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE5E92022A for ; Fri, 19 Feb 2016 06:52:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aWetn-00023r-4G; Fri, 19 Feb 2016 06:50:43 +0000 Received: from smtp6-v.fe.bosch.de ([2a03:cc00:ff0:100::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aWetj-00021j-AV for linux-arm-kernel@lists.infradead.org; Fri, 19 Feb 2016 06:50:41 +0000 Received: from vsmta12.fe.internet.bosch.com (unknown [10.4.98.52]) by imta24.fe.bosch.de (Postfix) with ESMTP id 9C97DD80217 for ; Fri, 19 Feb 2016 07:50:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=de.bosch.com; s=2015-01-21; t=1455864614; bh=NGTXlo7dm+XtLE1hMvqRzED2vavWa/fN0g29+mqOJQo=; l=10; h=From:From:Reply-To:Sender; b=S96e+FSpdTLwKTu9mJinMm7TYTj6KpWgkRy1jWB9KTydliU7pIsQbxt2cR7yZDk7y AgJy5Q7FiLfPMRGUEoJJQG/9uGe6TFRgfVCHH1v7Cn2pWUta751bcBrGQOQqiwa440 1GoRaN6ewPf//imKUqPMwYGqD3HcVOqidCOpgDz8= Received: from SI-HUB1001.de.bosch.com (vsgw24.fe.internet.bosch.com [10.4.98.24]) by vsmta12.fe.internet.bosch.com (Postfix) with ESMTP id 6A12D1B8037E for ; Fri, 19 Feb 2016 07:50:14 +0100 (CET) Received: from hi-z5661.hi.de.bosch.com (10.34.211.2) by SI-HUB1001.de.bosch.com (10.4.103.108) with Microsoft SMTP Server id 14.3.195.1; Fri, 19 Feb 2016 07:50:13 +0100 Received: from hi-z5661.hi.de.bosch.com (localhost [127.0.0.1]) by hi-z5661.hi.de.bosch.com (Postfix) with ESMTP id 72B07410EF; Fri, 19 Feb 2016 07:50:13 +0100 (CET) From: Dirk Behme To: , Subject: [PATCH v2] ARM: imx: Do L2 errata only if the L2 cache isn't enabled Date: Fri, 19 Feb 2016 07:50:12 +0100 Message-ID: <1455864612-12089-1-git-send-email-dirk.behme@de.bosch.com> X-Mailer: git-send-email 2.5.0 MIME-Version: 1.0 X-TM-AS-MML: disable X-TM-AS-Product-Ver: IMSS-7.1.0.1679-8.0.0.1202-22138.006 X-TMASE-MatchedRID: r0ILisMJH1jU4D7YCSb+lEhwlOfYeSqx75CEZqo4FcyuZgEQHmeEHKC3 hsj4rCqd/eBCguvP3h1BMlCV9gvTUehRubJazHK+rcaVXwBNpe8xmbT6wQT2a35tRMJpRVgEHi5 rbi6X2h3KwJG6rXlLlCY2nOuLWx53i34ke0DIAVwD2WXLXdz+Afi4nVERfgwdswOdry1CKakCWt l3fGE1f6o9sy4wKLqHgDLqnrRlXrZ8nn9tnqel2DsAVzN+Ov/soVKiwSmwishdTG8UhYvsNHUPF muwdBWLx/H1sknHOyUDyMYECovbbQ== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160218_225039_892969_20737D70 X-CRM114-Status: UNSURE ( 8.93 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -7.0 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcel Grosshans , Dirk Behme Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP All the generic L2 cache handling code is encapsulated by a check if the L2 cache is enabled. If it's enabled already, the code is skipped. The write to the L2-Cache controller from non-secure world causes an imprecise external abort. This is needed in scenarios where one of the cores runs an other OS, e.g. an RTOS. For the i.MX6 specific L2 cache handling we missed this check. Add it. Signed-off-by: Marcel Grosshans Signed-off-by: Dirk Behme --- Changes in v2: Update the commit message regarding the non-secure use case. arch/arm/mach-imx/system.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 51c3501..a600bd7 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -106,6 +106,9 @@ void __init imx_init_l2cache(void) goto out; } + if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN) + goto skip_if_enabled; + /* Configure the L2 PREFETCH and POWER registers */ val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); val |= 0x70800000; @@ -122,6 +125,7 @@ void __init imx_init_l2cache(void) val &= ~(1 << 30 | 1 << 23); writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); +skip_if_enabled: iounmap(l2x0_base); of_node_put(np);