From patchwork Mon Feb 22 14:01:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 8376731 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B2BBBC0553 for ; Mon, 22 Feb 2016 14:04:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C7FE620501 for ; Mon, 22 Feb 2016 14:04:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D64A420453 for ; Mon, 22 Feb 2016 14:04:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aXr3Q-0007q0-Tr; Mon, 22 Feb 2016 14:01:36 +0000 Received: from mail-lb0-x22e.google.com ([2a00:1450:4010:c04::22e]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aXr3K-0007ov-32 for linux-arm-kernel@lists.infradead.org; Mon, 22 Feb 2016 14:01:34 +0000 Received: by mail-lb0-x22e.google.com with SMTP id x1so82277570lbj.3 for ; Mon, 22 Feb 2016 06:01:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=lEfSENWOgNUr32i1RZ/D29lCcZ3za3BSvYgHJja9fwU=; b=MA+SxCOn5pbW8D73+Mvws78CKSgThGPq4fLSMFoZSjXQnCt+mbp4XYNrfQEH6R8ac8 GegO/u77tIUOGjnZK13mmJWB1bZWNfAfTb4yqUuFDoNaeCpxdKo69ciHKJtaOW3vL+/w buoeMoVBiC5bOoo9Q//GX64M6VAjsl02OE3sA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=lEfSENWOgNUr32i1RZ/D29lCcZ3za3BSvYgHJja9fwU=; b=fvW2dHalmjXVxy4+wBR03f7hsbz9QEm2+NldbgOOKFDBaRm96ri6x9GmNeoJcmd8UE amP6aMrZNzYykw6Cap4W05KZ7NQlTU37S1osw/A5iM0SbdEEpC1jdVTO3oiNJLERl/a4 Y2i7qQR3UIjCKH9lgMks7KKvSwqKoA72xCMnbUBYx9xI/V9T3f3sTzeEA+3rPJ+ylsOB axkNDqe3t2+S6xZ8xNPmq3IfgTByKcUMZqr+d6873TCRL733lSCb7CwdKaLYFfToQYJ+ GOYpfeBux8MKiSBlfKFtFF5FbHb1qUKAIFqXuRKiKsaWlGRCdYvM493Ihn3mVxx1+rQb akVw== X-Gm-Message-State: AG10YOSh9O9QrafSz75aLTm7GVu7mbL5W2l4dnGmXH0GRaGgTa/3oaifjrCPIdoXk6cNQnYY X-Received: by 10.112.159.10 with SMTP id wy10mr10280288lbb.114.1456149667306; Mon, 22 Feb 2016 06:01:07 -0800 (PST) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id pi5sm3252885lbb.41.2016.02.22.06.01.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Feb 2016 06:01:06 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Marc Zyngier Subject: [PATCH 1/3 v2] irqchip: gic/realview: support more RealView DCC variants Date: Mon, 22 Feb 2016 15:01:01 +0100 Message-Id: <1456149661-19118-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160222_060130_340204_53441138 X-CRM114-Status: GOOD ( 20.56 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Russell King , Pawel Moll , devicetree@vger.kernel.org, Linus Walleij , Will Deacon MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In the add-on file for the GIC dealing with the RealView family we currently only handle the PB11MPCore, let's extend this to manage the RealView EB ARM11MPCore as well. The Revision B of the ARM11MPCore core tile is a bit special and needs special handling as it moves a system control register around at random. Cc: Arnd Bergmann Cc: Marc Zyngier Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Acked-by: Rob Herring --- ChangeLog v1->v2: - Detect syscon register location based on the syscon compatible string instead of the GIC compatible string, just define one compatible string for the 11mp test chip GIC. - Consistently return -ENODEV This can be applied in isolation from the other patches so Marc one you're happy with it, please take it into the IRQchip tree. --- .../bindings/interrupt-controller/arm,gic.txt | 1 + drivers/irqchip/irq-gic-realview.c | 44 +++++++++++++++++++--- 2 files changed, 39 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt index 5a1cb4bc3dfe..793c20ff8fcc 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt @@ -16,6 +16,7 @@ Main node required properties: "arm,cortex-a15-gic" "arm,cortex-a7-gic" "arm,cortex-a9-gic" + "arm,eb11mp-gic" "arm,gic-400" "arm,pl390" "arm,tc11mp-gic" diff --git a/drivers/irqchip/irq-gic-realview.c b/drivers/irqchip/irq-gic-realview.c index aa46eb280a7f..54c296401525 100644 --- a/drivers/irqchip/irq-gic-realview.c +++ b/drivers/irqchip/irq-gic-realview.c @@ -10,7 +10,8 @@ #include #define REALVIEW_SYS_LOCK_OFFSET 0x20 -#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 +#define REALVIEW_SYS_PLD_CTRL1 0x74 +#define REALVIEW_EB_REVB_SYS_PLD_CTRL1 0xD8 #define VERSATILE_LOCK_VAL 0xA05F #define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24) #define PLD_INTMODE_LEGACY 0x0 @@ -18,26 +19,57 @@ #define PLD_INTMODE_NEW_NO_DCC BIT(23) #define PLD_INTMODE_FIQ_ENABLE BIT(24) +/* For some reason RealView EB Rev B moved this register */ +static const struct of_device_id syscon_pldset_of_match[] = { + { + .compatible = "arm,realview-eb11mp-revb-syscon", + .data = (void *)REALVIEW_EB_REVB_SYS_PLD_CTRL1, + }, + { + .compatible = "arm,realview-eb11mp-revc-syscon", + .data = (void *)REALVIEW_SYS_PLD_CTRL1, + }, + { + .compatible = "arm,realview-eb-syscon", + .data = (void *)REALVIEW_SYS_PLD_CTRL1, + }, + { + .compatible = "arm,realview-pb11mp-syscon", + .data = (void *)REALVIEW_SYS_PLD_CTRL1, + }, + {}, +}; + static int __init realview_gic_of_init(struct device_node *node, struct device_node *parent) { static struct regmap *map; + struct device_node *np; + const struct of_device_id *gic_id; + u32 pld1_ctrl; + + np = of_find_matching_node_and_match(NULL, syscon_pldset_of_match, + &gic_id); + if (!np) + return -ENODEV; + pld1_ctrl = (u32)gic_id->data; /* The PB11MPCore GIC needs to be configured in the syscon */ - map = syscon_regmap_lookup_by_compatible("arm,realview-pb11mp-syscon"); + map = syscon_node_to_regmap(np); if (!IS_ERR(map)) { /* new irq mode with no DCC */ regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, VERSATILE_LOCK_VAL); - regmap_update_bits(map, REALVIEW_PB11MP_SYS_PLD_CTRL1, + regmap_update_bits(map, pld1_ctrl, PLD_INTMODE_NEW_NO_DCC, PLD_INTMODE_MASK); regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000); - pr_info("TC11MP GIC: set up interrupt controller to NEW mode, no DCC\n"); + pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n"); } else { - pr_err("TC11MP GIC setup: could not find syscon\n"); - return -ENXIO; + pr_err("RealView GIC setup: could not find syscon\n"); + return -ENODEV; } return gic_of_init(node, parent); } IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init); +IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init);