From patchwork Wed Feb 24 15:14:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 8408871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E9519C0553 for ; Wed, 24 Feb 2016 15:19:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 08E79202D1 for ; Wed, 24 Feb 2016 15:19:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F9A820266 for ; Wed, 24 Feb 2016 15:19:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aYbC9-0003Zr-2M; Wed, 24 Feb 2016 15:17:41 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aYb9q-00085V-AG for linux-arm-kernel@lists.infradead.org; Wed, 24 Feb 2016 15:15:24 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 53D5917C2; Wed, 24 Feb 2016 16:14:38 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (AToulouse-657-1-984-111.w86-217.abo.wanadoo.fr [86.217.138.111]) by mail.free-electrons.com (Postfix) with ESMTPSA id 1D10511D; Wed, 24 Feb 2016 16:14:38 +0100 (CET) From: Thomas Petazzoni To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala Subject: [PATCH v2 6/6] clk: mvebu: add AP806 ring clock driver Date: Wed, 24 Feb 2016 16:14:26 +0100 Message-Id: <1456326866-30854-7-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1456326866-30854-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1456326866-30854-1-git-send-email-thomas.petazzoni@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160224_071518_898037_D2526BDC X-CRM114-Status: GOOD ( 18.78 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lior Amsalem , Andrew Lunn , Yehuda Yitschak , Jason Cooper , Nadav Haklai , Neta Zur Hershkovits , Gregory Clement , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This commit adds a new driver to handle the ring clocks found in the AP806 HW block, which is the core block of all Armada 7K and 8K Marvell 64-bits processors. Those ring clocks are derived from the core ring clock handled by the AP806 core clock driver. The ring clocks are used by various peripherals inside the AP806. Signed-off-by: Thomas Petazzoni --- drivers/clk/mvebu/Kconfig | 3 ++ drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/ap806-ring.c | 74 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+) create mode 100644 drivers/clk/mvebu/ap806-ring.c diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig index fd84172..5d30aac 100644 --- a/drivers/clk/mvebu/Kconfig +++ b/drivers/clk/mvebu/Kconfig @@ -45,3 +45,6 @@ config ORION_CLK config ARMADA_AP806_CORE_CLK bool + +config ARMADA_AP806_RING_CLK + bool diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile index db5c28c..48ca2d3 100644 --- a/drivers/clk/mvebu/Makefile +++ b/drivers/clk/mvebu/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o obj-$(CONFIG_ARMADA_38X_CLK) += armada-38x.o obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o obj-$(CONFIG_ARMADA_AP806_CORE_CLK) += ap806-core.o +obj-$(CONFIG_ARMADA_AP806_RING_CLK) += ap806-ring.o obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o diff --git a/drivers/clk/mvebu/ap806-ring.c b/drivers/clk/mvebu/ap806-ring.c new file mode 100644 index 0000000..f980192 --- /dev/null +++ b/drivers/clk/mvebu/ap806-ring.c @@ -0,0 +1,74 @@ +/* + * Marvell Armada AP806 ring clocks + * + * Copyright (C) 2016 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "ap806-ring-clk: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#define AP806_RING_DIV_CLK_REG 0x250 + +#define AP806_RING_DIV_NUM 5 + +static struct clk *ap806_ring_clks[AP806_RING_DIV_NUM]; + +static struct clk_onecell_data ap806_ring_clk_data = { + .clks = ap806_ring_clks, + .clk_num = AP806_RING_DIV_NUM, +}; + +static void __init ap806_ring_clk_init(struct device_node *np) +{ + struct regmap *regmap; + const char *parent; + u32 reg; + int i; + + regmap = syscon_node_to_regmap(np->parent); + if (IS_ERR(regmap)) { + pr_err("cannot get regmap\n"); + return; + } + + if (regmap_read(regmap, AP806_RING_DIV_CLK_REG, ®)) { + pr_err("cannot read from regmap\n"); + return; + } + + parent = of_clk_get_parent_name(np, 0); + + for (i = 0; i < AP806_RING_DIV_NUM; i++) { + unsigned long divider; + const char *name; + + /* Each clock is represented by 6 bits */ + divider = (reg >> (6 * i)) & 0x3f; + + of_property_read_string_index(np, "clock-output-names", + i, &name); + + ap806_ring_clks[i] = + clk_register_fixed_factor(NULL, name, parent, + 0, 1, divider); + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_ring_clk_data); +} + +CLK_OF_DECLARE(ap806_ring_clk, "marvell,armada-ap806-ring-clock", + ap806_ring_clk_init);