From patchwork Thu Mar 3 11:40:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 8491881 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3F84EC0553 for ; Thu, 3 Mar 2016 11:50:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 31BC020295 for ; Thu, 3 Mar 2016 11:50:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2A671201EF for ; Thu, 3 Mar 2016 11:50:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1abRjI-0005P6-Je; Thu, 03 Mar 2016 11:47:40 +0000 Received: from mail-wm0-x232.google.com ([2a00:1450:400c:c09::232]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1abRcr-0006yk-HM for linux-arm-kernel@lists.infradead.org; Thu, 03 Mar 2016 11:41:08 +0000 Received: by mail-wm0-x232.google.com with SMTP id p65so30674697wmp.1 for ; Thu, 03 Mar 2016 03:40:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rhJTOzvqmxIB4K3BRO0pzvIUpdXCOYV4vMm1ZYxD4LE=; b=m5YZ3r/CFlG8DGyxtzGId/lCTKLSY1UVFVr+jc03JHX95OfC+6ex7LWzX20hWlttCn c3oG/lk2C9SjQ/5klFzUZYrRjIqgiPcTRnVX3Y4EXD591C3mBmRlQUu5wuzwalrIVrOw mPde8I3i1jjszTpM7qwTLHDw8Bn+/y0Q2T2OBaZb6fknjAjF1xbtnsNicIHohD4U6oaX OuMKdJKO/xO17RWNuEirLewuGkVCjKyXK1KIDofGTKw7/fwNB5hS2osiwcOHmaPY5i3l tef52e5FF55xHYvKaa+UZQMbExiFOId+AFnRWUDd+n5Gn8NkyHHUPMT+z+ZrcDstu/oN 8HHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rhJTOzvqmxIB4K3BRO0pzvIUpdXCOYV4vMm1ZYxD4LE=; b=Fy3xZzqKD3XdI3AcJFm1CoCNz+7zM5cfWHwLfhPaz+6ZKoaEC53K+Ysb4Lt8G1Eaxs baBHuaJB6F3P7yhrtKpI3n4hN/vgFB6iixeDccBtKTq4p2h+d2Og6OYZj2Ew8ersrE18 d/Mmw/969ijBUdVl5wA5mE0/NeSqo8ffW9Ht6mNg8al84+7u1Njt96LGRPYLE05JnUT6 01o3iLFNzUO1L/89bZXNtSs0DA+ubq1fznkkPFpZ+hJD7t4iwWPL4uLemqbdphu3sos7 UYe6agvjY5ZgWtcQt8b7LltUcfVqaSh/ivfZkZVuxJ3d2RP9+A/MIJJ+fYanKRsZePP+ rgow== X-Gm-Message-State: AD7BkJIJiEeVRBwGahOLomzGynKISD115dKwZGaq8+kBN+m7jELaPlz0/dr/K+pdw826+4uQ X-Received: by 10.28.1.196 with SMTP id 187mr2949310wmb.68.1457005239924; Thu, 03 Mar 2016 03:40:39 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id j18sm8559725wmd.2.2016.03.03.03.40.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 03 Mar 2016 03:40:39 -0800 (PST) From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 11/17] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings Date: Thu, 3 Mar 2016 12:40:04 +0100 Message-Id: <1457005210-18485-12-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> References: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160303_034102_004047_D1FB0BD8 X-CRM114-Status: GOOD ( 17.47 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Neil Armstrong --- .../devicetree/bindings/gpio/gpio_oxnas.txt | 27 ++++++ .../bindings/pinctrl/plxtech,pinctrl.txt | 100 +++++++++++++++++++++ 2 files changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio_oxnas.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt new file mode 100644 index 0000000..0ef6c55 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt @@ -0,0 +1,27 @@ +PLX Technology OXNAS SoC GPIO Controller +========================================== + +Required properties: +- compatible: "plxtech,nas782x-gpio". +- reg: Should contain GPIO controller registers location and length +- interrupts: Should be the port interrupt shared by all the pins. +- #gpio-cells: Should be two. The first cell is the pin number and + the second cell is used to specify optional parameters (currently + unused). +- gpio-controller: Marks the device node as a GPIO controller. + +optional properties: +- #gpio-lines: Number of gpio if absent 32. + + +Example: + gpio0: gpio@000000 { + compatible = "plxtech,nas782x-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-lines = <32>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt new file mode 100644 index 0000000..30f013f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt @@ -0,0 +1,100 @@ +PLX Technology OXNAS SoC Pinmux Controller +========================================== + +The OXNAS Pinmux Controller, enables the IC to share one PAD to several +functional blocks. The sharing is done by multiplexing the PAD input/output +signals. For each PAD there are up to 8 muxing options (called periph modes). +Since different modules require different PAD settings +(like pull up, keeper, etc) the contoller controls also the PAD settings +parameters. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +OXNAS pin configuration node is a node of a group of pins which can be +used for a specific device or function. This node represents both mux and config +of the pins in that group. The 'pins' selects the function mode(also named pin +mode) this pin can work on and the 'config' configures various pad settings +such as pull-up, multi drive, etc. + +Required properties for iomux controller: +- compatible: "plxtech,nas782x-pinctrl" or "plxtech,ox810se-pinctrl" +- plxtech,mux-mask: array of mask (periph per bank) to describe if a pin can be + configured in this periph mode. All the periph and bank need to be describe. +- plxtech,sys-ctrl: a phandle to the system controller syscon node + +How to create such array: + +Each column will represent the possible peripheral of the pinctrl +Each line will represent a pio bank + +For example : +Peripheral: 2 ( A and B) +Bank: 2 (A, B and C) +=> + + /* A B */ + 0xffffffff 0xffc00c3b /* pioA */ + 0xffffffff 0x7fff3ccf /* pioB */ + +For each peripheral/bank we will descibe in a u32 if a pin can be +configured in it by putting 1 to the pin bit (1 << pin) + +Required properties for pin configuration node: +- plxtech,pins: 4 integers array, represents a group of pins mux and config + setting. The format is plxtech,pins = . + The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... + PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... + +Bits used for CONFIG: + - None Yet + +Examples: + +pinctrl: pinctrl { + compatible = "plxtech,nas782x-pinctrl", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Regmap for sys registers */ + plxtech,sys-ctrl = <&sys>; + + /* Default, all-open mux-map */ + plxtech,mux-mask = < + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF + >; + + uart0 { + pinctrl_uart0: uart0 { + plxtech,pins = <0 31 3 0 + 0 32 3 0>; + }; + pinctrl_uart0_modem: uart0_modem { + plxtech,pins = <0 27 3 0 + 0 28 3 0 + 0 29 3 0 + 0 30 3 0 + 0 33 3 0 + 0 34 3 0>; + }; + }; +}; + +uart0: uart@200000 { + compatible = "ns16550a"; + reg = <0x200000 0x100000>; + clocks = <&sysclk>; + interrupts = <23>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 17>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +};