From patchwork Thu Mar 3 11:39:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 8491571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 50E099F2F0 for ; Thu, 3 Mar 2016 11:44:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 027E820373 for ; Thu, 3 Mar 2016 11:44:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B194F202E5 for ; Thu, 3 Mar 2016 11:44:19 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1abRdI-0007DU-Ui; Thu, 03 Mar 2016 11:41:28 +0000 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1abRci-0006yS-SL for linux-arm-kernel@lists.infradead.org; Thu, 03 Mar 2016 11:40:54 +0000 Received: by mail-wm0-x230.google.com with SMTP id l68so30777759wml.0 for ; Thu, 03 Mar 2016 03:40:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=M/SLERVLoy+A3KUq1qUA2Zbzhwkx9+ccOBKVnuGkyZs=; b=a/nTiWhHgnEth5IMK7figstxs3q77KBwcNBrqCIIy0AVj0lnlISNm79tYSiurHPIQ6 7NnpJbrPBSnSo08clewIgd58ilMzxGyD4wx1lMfQ8bc/0Wg1EkK5cAgRV/7PUkLmIAsg 2fr9SveiLuZCnyiRaREW1yY/a1ueRHLH0OEU6NJ2uVwKwZfFQEVADhoLwHiwlUfBMQd/ f0ogltS2rMgIIMOTN67Pucb9+N8LIMr/WKgFow7JO8z2rI0WibXF86O1S9woHjN+OQXl OR7n3vjzimHV2GjfWoNNMWA5yEEQ/Md6IPfuZFETudIVPllvu5KcAg2CCoxlnUswHUyx Ji2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=M/SLERVLoy+A3KUq1qUA2Zbzhwkx9+ccOBKVnuGkyZs=; b=YM5XJ0u3ErbFr3G4Pi6e1iRIF3A6a9gTxEdYKedtK0teuV1Sw0yVO3M7hakGWgNvTQ IZTBvNBcXdV833ylmhz8dBaychP5jUVya6CSjAF2pXvXMOpAlYuFiPCvUzUCTDn7v7id 3mfs2lgMyxK+epdaCBZHvqUUYq/Xq5OUVoyzkDGiAx7aHQlRW11RBvthL6CodzBS49VS TS74kfthrTlqQGbDLK/90iFiqe3D/wU3vK08Dpn0W556SHQja8HZipPB0s4qmywdzPFm hvHS2+WNhvZOLRxSZDtlc10tUvP5SginSR6Djovk67ftz8c5d7lQgDuqh3XXZdQmoIb0 sbIg== X-Gm-Message-State: AD7BkJIQynx/ylCTfxtQL39pK3HdHQfmIhvIi2Ee0C3jj/MBWhdkKZmwoop/+hMiN1RXIZRA X-Received: by 10.28.1.9 with SMTP id 9mr5012619wmb.97.1457005231280; Thu, 03 Mar 2016 03:40:31 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id j18sm8559725wmd.2.2016.03.03.03.40.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 03 Mar 2016 03:40:30 -0800 (PST) From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com Subject: [PATCH 02/17] irqchip: Add PLX Technology RPS IRQ Controller Date: Thu, 3 Mar 2016 12:39:55 +0100 Message-Id: <1457005210-18485-3-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> References: <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160303_034053_139119_8126007B X-CRM114-Status: GOOD ( 17.73 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ma Haijun , Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add PLX Technology RPS IRQ Controller as irqchip driver. CC: Ma Haijun Signed-off-by: Neil Armstrong --- drivers/irqchip/Kconfig | 5 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-rps.c | 128 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 134 insertions(+) create mode 100644 drivers/irqchip/irq-rps.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index fb50911..7892c1a 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -135,6 +135,11 @@ config PIC32_EVIC select GENERIC_IRQ_CHIP select IRQ_DOMAIN +config PLXTECH_RPS + bool + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + config RENESAS_INTC_IRQPIN bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 18caacb..3eec3a0 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_I8259) += irq-i8259.o obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o +obj-$(CONFIG_PLXTECH_RPS) += irq-rps.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o diff --git a/drivers/irqchip/irq-rps.c b/drivers/irqchip/irq-rps.c new file mode 100644 index 0000000..bcd4a31 --- /dev/null +++ b/drivers/irqchip/irq-rps.c @@ -0,0 +1,128 @@ +/* + * drivers/irqchip/irq-rps.c + * + * Copyright (C) 2009 Oxford Semiconductor Ltd + * Copyright (C) 2013 Ma Haijun + * Copyright (C) 2016 Neil Armstrong + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct rps_chip_data { + void __iomem *base; + struct irq_domain *domain; +} rps_data; + +enum { + RPS_IRQ_COUNT = 32, + + RPS_STATUS = 0, + RPS_RAW_STATUS = 4, + RPS_UNMASK = 8, + RPS_MASK = 0xc, +}; + +/* Routines to acknowledge, disable and enable interrupts */ +static void rps_mask_irq(struct irq_data *d) +{ + u32 mask = BIT(d->hwirq); + + iowrite32(mask, rps_data.base + RPS_MASK); +} + +static void rps_unmask_irq(struct irq_data *d) +{ + u32 mask = BIT(d->hwirq); + + iowrite32(mask, rps_data.base + RPS_UNMASK); +} + +static void rps_ack_irq(struct irq_data *d) +{ + /* NOP */ +} + +static void __exception_irq_entry handle_irq(struct pt_regs *regs) +{ + u32 irqstat; + int hwirq; + + irqstat = ioread32(rps_data.base + RPS_STATUS); + hwirq = __ffs(irqstat); + + do { + handle_IRQ(irq_find_mapping(rps_data.domain, hwirq), regs); + + irqstat = ioread32(rps_data.base + RPS_STATUS); + hwirq = __ffs(irqstat); + } while (irqstat); +} + +int __init rps_of_init(struct device_node *node, struct device_node *parent) +{ + int ret; + struct irq_chip_generic *gc; + + if (WARN_ON(!node)) + return -ENODEV; + + rps_data.base = of_iomap(node, 0); + WARN(!rps_data.base, "unable to map rps registers\n"); + + rps_data.domain = irq_domain_add_linear(node, RPS_IRQ_COUNT, + &irq_generic_chip_ops, + NULL); + if (!rps_data.domain) { + pr_err("%s: could add irq domain\n", + node->full_name); + return -ENOMEM; + } + + ret = irq_alloc_domain_generic_chips(rps_data.domain, RPS_IRQ_COUNT, 1, + "RPS", handle_level_irq, + 0, 0, IRQ_GC_INIT_NESTED_LOCK); + if (ret) { + pr_err("%s: could not allocate generic chip\n", + node->full_name); + irq_domain_remove(rps_data.domain); + return -EINVAL; + } + + gc = irq_get_domain_generic_chip(rps_data.domain, 0); + gc->chip_types[0].chip.irq_ack = rps_ack_irq; + gc->chip_types[0].chip.irq_mask = rps_mask_irq; + gc->chip_types[0].chip.irq_unmask = rps_unmask_irq; + + /* Disable all IRQs */ + iowrite32(~0, rps_data.base + RPS_MASK); + + set_handle_irq(handle_irq); + + pr_info("Registered %d rps interrupts\n", RPS_IRQ_COUNT); + + return 0; +} + +IRQCHIP_DECLARE(nas782x, "plxtech,nas782x-rps", rps_of_init);