From patchwork Tue Mar 8 06:33:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 8529951 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 45DE79F7CA for ; Tue, 8 Mar 2016 06:38:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5B3ED2014A for ; Tue, 8 Mar 2016 06:38:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2502C2015E for ; Tue, 8 Mar 2016 06:38:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1adBGF-0004nL-0N; Tue, 08 Mar 2016 06:36:51 +0000 Received: from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1adBG6-0004cG-Lc for linux-arm-kernel@lists.infradead.org; Tue, 08 Mar 2016 06:36:45 +0000 Received: by mail-pf0-x22d.google.com with SMTP id 63so5913293pfe.3 for ; Mon, 07 Mar 2016 22:36:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=AphLxo/QTcojl7t/e5qSmCIipRMx6lHNURwuVfSx2Jdj0U/UYI/kjbtXHBXDul3YQ2 mjqMGOjdr7cyUXINqjszEQA4jCOVYHFeoz3xryMxOEWQ4pWKNphj7Z7gcqElQkDmEjFc G4aEv7pKpphn0v4usVHorlYs/0SA3UtA5mA3U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=GEYSkWpPQIN+vFV/Pkl/Pm1Md6P35Glnq4nVzD9EXOdWsllYtzCmmUABWHLh6Cnozm LCgDl0m9iY9FnyfJz49mRBBbXWp8axuzY1dzMWd/z4IMPFcvzJm8DEy6XFbDu1LAyajI 9Fv55JDZpA67WXaC5SM9g4c9MYZ867sqbZQdA1agWyns+I5TfMrPfG1YgsCTX4+cJODZ +g7i9Njn3MQ9637DquvtS8NGAIrMx0/W6FWUFdiWhNcCmxWyDk2TtE97eWOuiq+8PwFD x/bIAQZyb9zc+Ya4BRQm2sf6PdrjiMrxqjWWYydpF+OQBaIhhqOKfQObIvmvGQ86NBeE Xgvg== X-Gm-Message-State: AD7BkJK5XglFEXhEwaPokKSNnjT1Q1woB+mfviy0i5UgCadKkzaH+gEHQGVi10orFt1fTiYw X-Received: by 10.98.17.208 with SMTP id 77mr38563554pfr.37.1457418981874; Mon, 07 Mar 2016 22:36:21 -0800 (PST) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id fn3sm1986372pab.20.2016.03.07.22.36.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Mar 2016 22:36:20 -0800 (PST) From: Chunyan Zhang To: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Subject: [RESEND PATCH V4 3/4] coresight-stm: Bindings for System Trace Macrocell Date: Tue, 8 Mar 2016 14:33:54 +0800 Message-Id: <1457418835-31417-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457418835-31417-1-git-send-email-zhang.chunyan@linaro.org> References: <1457418835-31417-1-git-send-email-zhang.chunyan@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160307_223643_096767_D692A528 X-CRM114-Status: GOOD ( 11.16 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, Michael.Williams@arm.com, linux-doc@vger.kernel.org, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, tor@ti.com, mike.leach@arm.com, linux-api@vger.kernel.org, pratikp@codeaurora.org, nicolas.guion@st.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mathieu Poirier The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 62938eb..93147c0c 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -19,6 +19,7 @@ its hardware characteristcs. - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -36,6 +37,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -202,3 +211,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name.