From patchwork Fri Mar 11 10:55:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 8564641 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B01FE9F6E4 for ; Fri, 11 Mar 2016 11:01:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BFA822034B for ; Fri, 11 Mar 2016 11:01:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E0A6720340 for ; Fri, 11 Mar 2016 11:01:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aeKnE-0000Nt-NW; Fri, 11 Mar 2016 10:59:40 +0000 Received: from mail-pa0-f67.google.com ([209.85.220.67]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aeKmG-0007pt-C0; Fri, 11 Mar 2016 10:58:46 +0000 Received: by mail-pa0-f67.google.com with SMTP id fl4so7993981pad.2; Fri, 11 Mar 2016 02:58:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v4FzimVV5uVjSq6beUJ/dGMt2a4P3U8tWF/je3fwYFw=; b=ivLv50/WsFX5kkZsThpf4qAJ/cvU1xBZ3taPtJbPlZb2PNgsn6j8nU71QplG2+I9JW NXGFNEeX8YQ/3rhip6AReu+5pDPcI4GOHXV8E5URyXl2KqOywIWv1IkujfeTOXBw80Nb b6NXYZL1CwVpydHGqx/mVyCXL61wyjwGGmub8KSF9wU75+TouzCEC0T76sWdH1hZIdpU fml8UI9oDZpQGgANkrU5v0qbtkHOJKhJtkqjxdF0XwvF6w+4e9WtLtN2BEnhb2xfxogB MI0XYuuctHhDv9JEp2kQQK8nhv79rYTh+4CnjILZwmuE1NaTXdeflZj6t+4VKzBjz/5c HW0w== X-Gm-Message-State: AD7BkJLX1vlSTa3T4rz//D+AP20oGEBMoSqLjhDsIYomkqWDM3uadHBFJIFo47tJ66VAaA== X-Received: by 10.67.5.133 with SMTP id cm5mr13816090pad.133.1457693899190; Fri, 11 Mar 2016 02:58:19 -0800 (PST) Received: from localhost.localdomain ([58.22.7.114]) by smtp.gmail.com with ESMTPSA id x64sm12042302pfa.72.2016.03.11.02.58.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 Mar 2016 02:58:17 -0800 (PST) From: Caesar Wang To: Heiko Stuebner , "David S. Miller" , Rob Herring Subject: [PATCH 5/6] clk: rockchip: rk3036: fix and add node id for emac clock Date: Fri, 11 Mar 2016 18:55:30 +0800 Message-Id: <1457693731-6966-6-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457693731-6966-1-git-send-email-wxt@rock-chips.com> References: <1457693731-6966-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160311_025840_891116_DB354D3F X-CRM114-Status: GOOD ( 10.48 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Pawel Moll , zhengxing , Ian Campbell , Michael Turquette , Kumar Gala , Stephen Boyd , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, keescook@google.com, linux-clk@vger.kernel.org, leozwang@google.com, Caesar Wang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: zhengxing In the emac driver, we need to refer HCLK_MAC since there are only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clocks are under the GPLL, and it is unable to provide the accurate rate for mac_ref which need to 50MHz probability, we should let it under the DPLL and are able to set the freq which integer multiples of 50MHz, so we add these emac node for reference. Signed-off-by: Xing Zheng Signed-off-by: Caesar Wang --- drivers/clk/rockchip/clk-rk3036.c | 9 ++++++--- include/dt-bindings/clock/rk3036-cru.h | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 0703c8f..27c35fa 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -348,8 +348,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, RK2928_CLKGATE_CON(10), 5, GFLAGS), - COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, - RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), + MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0, + RK2928_CLKSEL_CON(21), 0, 2, MFLAGS), + DIV(0, "mac_pll_src", "mac_pll_pre", 0, + RK2928_CLKSEL_CON(21), 9, 5, DFLAGS), + MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), @@ -408,7 +411,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), - GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS), + GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), /* pclk_peri gates */ GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index ebc7a7b..de44109 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -54,6 +54,7 @@ #define SCLK_PVTM_VIDEO 125 #define SCLK_MAC 151 #define SCLK_MACREF 152 +#define SCLK_MACPLL 153 #define SCLK_SFC 160 /* aclk gates */ @@ -92,6 +93,7 @@ #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 +#define HCLK_MAC 460 #define HCLK_I2S 462 #define HCLK_LCDC 465 #define HCLK_ROM 467