From patchwork Thu Mar 17 20:18:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jayachandran C." X-Patchwork-Id: 8614251 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7E4899FC32 for ; Thu, 17 Mar 2016 20:35:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 94FFD2034A for ; Thu, 17 Mar 2016 20:35:20 +0000 (UTC) Received: from bombadil.infradead.org (unknown [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C2A9720328 for ; Thu, 17 Mar 2016 20:35:19 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ageUQ-00071e-1W; Thu, 17 Mar 2016 20:25:50 +0000 Received: from mail-gw3-out.broadcom.com ([216.31.210.64]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ageTY-0005Z5-Jj for linux-arm-kernel@lists.infradead.org; Thu, 17 Mar 2016 20:24:57 +0000 X-IronPort-AV: E=Sophos;i="5.24,351,1455004800"; d="scan'208";a="90327993" Received: from mail-irv-18.broadcom.com ([10.15.198.37]) by mail-gw3-out.broadcom.com with ESMTP; 17 Mar 2016 13:31:19 -0700 Received: from mail-irva-13.broadcom.com (mail-irva-13.broadcom.com [10.11.16.103]) by mail-irv-18.broadcom.com (Postfix) with ESMTP id 6055982025; Thu, 17 Mar 2016 13:24:38 -0700 (PDT) Received: from lc-blr-136.ban.broadcom.com (unknown [10.131.60.136]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id B91AE40FEA; Thu, 17 Mar 2016 13:24:08 -0700 (PDT) From: Jayachandran C To: Bjorn Helgaas , Tomasz Nowicki , rafael@kernel.org Subject: [RFC PATCH 4/4] ACPI: PCI: Add raw_pci_read/write operations Date: Fri, 18 Mar 2016 01:48:33 +0530 Message-Id: <1458245913-17211-5-git-send-email-jchandra@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458245913-17211-1-git-send-email-jchandra@broadcom.com> References: <1458245913-17211-1-git-send-email-jchandra@broadcom.com> In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160317_132456_781053_BDC6AC05 X-CRM114-Status: GOOD ( 10.98 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linaro-acpi@lists.linaro.org, linux-pci@vger.kernel.org, Will Deacon , okaya@codeaurora.org, wangyijing@huawei.com, Lorenzo Pieralisi , David Daney , linux-acpi@vger.kernel.org, robert.richter@caviumnetworks.com, Catalin Marinas , Liviu.Dudau@arm.com, Arnd Bergmann , Stefano Stabellini , Jon Masters , msalter@redhat.com, Marcin Wojtas , linux-arm-kernel@lists.infradead.org, Jayachandran C , linux-kernel@vger.kernel.org, Hanjun Guo , Suravee.Suthikulpanit@amd.com, jiang.liu@linux.intel.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RDNS_NONE,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Provide implementations of raw_pci_read and raw_pci_write needed by ACPI. We already maintain a gen_acpi_pci_roots list with all the ACPI PCI controllers, so we walk thru this list to see if there is an existing mapping. If there is one, we can use the generic config space access. If there is no existing mapping, create a temporary mapping with information available in the saved MCFG table and use it to do raw config space access. Signed-off-by: Jayachandran C --- drivers/acpi/pci_gen_host.c | 87 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/acpi/pci_gen_host.c b/drivers/acpi/pci_gen_host.c index a43f2cee..b5472f0 100644 --- a/drivers/acpi/pci_gen_host.c +++ b/drivers/acpi/pci_gen_host.c @@ -245,3 +245,90 @@ void __init pci_mmcfg_late_init(void) mcfgsav.cfg, mcfgsav.size); } } + +/* + * First walk thru the root infos of all the known ACPI PCI + * controllers to see if there is an existing mapping and + * use it if we find one. + * Otherwise check the MCFG table and setup a temporary mapping + */ +static int raw_pci_op(int domain, unsigned int busn, unsigned int devfn, + int reg, int len, u32 *val, bool write) +{ + void __iomem *m; + struct acpi_pci_generic_root_info *ri; + struct acpi_pci_root *root; + bool tmpmap = false; + int i, ret = PCIBIOS_DEVICE_NOT_FOUND; + + mutex_lock(&gen_acpi_pci_lock); + list_for_each_entry(ri, &gen_acpi_pci_roots, node) { + root = ri->common.root; + if (domain == root->segment && + busn >= (u8)root->secondary.start && + busn <= (u8)root->secondary.end) { + m = pci_generic_map_bus(ri->cfg, busn, devfn, reg); + if (m) + goto found; + else + goto err_out; + } + } + + /* not found in existing root buses, check in mcfg */ + i = mcfg_lookup(domain, busn, busn); + if (i < 0) + goto err_out; + + /* get a temporary mapping */ + busn -= mcfgsav.cfg[i].bus_start; + m = ioremap(mcfgsav.cfg[i].addr + (busn << 20 | devfn << 12), 1 << 12); + if (!m) + goto err_out; + tmpmap = true; + m += reg; +found: + if (write) { + switch (len) { + case 1: + writeb(*val, m); + break; + case 2: + writew(*val, m); + break; + case 4: + writel(*val, m); + break; + } + } else { + switch (len) { + case 1: + *val = readb(m); + break; + case 2: + *val = readw(m); + break; + case 4: + *val = readl(m); + break; + } + } + if (tmpmap) + iounmap(m); + ret = 0; +err_out: + mutex_unlock(&gen_acpi_pci_lock); + return ret; +} + +int raw_pci_read(unsigned int domain, unsigned int busn, unsigned int devfn, + int reg, int len, u32 *val) +{ + return raw_pci_op(domain, busn, devfn, reg, len, val, false); +} + +int raw_pci_write(unsigned int domain, unsigned int busn, unsigned int devfn, + int reg, int len, u32 val) +{ + return raw_pci_op(domain, busn, devfn, reg, len, &val, true); +}