From patchwork Tue Mar 22 20:23:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 8645141 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A6B17C0553 for ; Tue, 22 Mar 2016 20:29:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 885192014A for ; Tue, 22 Mar 2016 20:29:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7A67C2012D for ; Tue, 22 Mar 2016 20:29:06 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aiStc-0003Ur-Jw; Tue, 22 Mar 2016 20:27:20 +0000 Received: from mail-io0-x236.google.com ([2607:f8b0:4001:c06::236]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aiSqe-00089E-EH for linux-arm-kernel@lists.infradead.org; Tue, 22 Mar 2016 20:24:18 +0000 Received: by mail-io0-x236.google.com with SMTP id m184so255401785iof.1 for ; Tue, 22 Mar 2016 13:23:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K07eSj6SbKssd1alyY/c3h0kznYCA4oQdpEb45Gs1qs=; b=DE1MvYnG2XtV+kkNdRjW+GVLPRWp2cZLLD2TI0NAbWIEs/al4GXI7NdW7k4PK/nhrN zzfDhqgK+7NEFagpH0gIXAr2jggjagkmanKQXe52FPf+5tcwoNE4RgXkexirlNwJxGGz feRE0T0ZMCDc/v7FPaMoOip8mv56Sya9S6Zcg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K07eSj6SbKssd1alyY/c3h0kznYCA4oQdpEb45Gs1qs=; b=I0FSMA/7pir8Ueyk/gV7R08/hI8Y+oCnFCBgWl9GEuSzdiB4dC0Fsg9VNFRMGZrBip qebeEwVAl+4NS9h69A4CB5o/J+6XJwllZe0LJ2HeaYgYwQrG7bHVwgZiJl706iqFNqmV h/byKJfxWy0HdNJhd1ZHOErYLFZKP00NY9LBubdLZ7j0h0Te5ztX+Xt4xRGb6ZBP8fe/ V4Hw7QZBY3ohQd4GSFEbmTL4YTSpKWqc3s5Ouyuxct5nikJXGmcJylDpXjha789sjK8k 5sK4wM4bTKnanRZIxNc0oN23hTxlkvL3Yyy8gRhEa/MkpI6FIy1Ij6GBHRU+bIZaYVkE eR7A== X-Gm-Message-State: AD7BkJLVBTaop+wbW5FrRGYG6JjO8t8jq3iUZ6uXnNPV+PKb69z5oaGFnt/SWoW4jiLuFWg0 X-Received: by 10.107.4.10 with SMTP id 10mr41323999ioe.22.1458678235463; Tue, 22 Mar 2016 13:23:55 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id xo2sm8092061igb.0.2016.03.22.13.23.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Mar 2016 13:23:54 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 09/14] coresight: tmc: adding mode of operation for link/sinks Date: Tue, 22 Mar 2016 14:23:17 -0600 Message-Id: <1458678202-3447-10-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1458678202-3447-1-git-send-email-mathieu.poirier@linaro.org> References: <1458678202-3447-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160322_132416_696102_87C37EB6 X-CRM114-Status: GOOD ( 17.33 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Moving tmc_drvdata::enable to a local_t mode. That way the sink interface is aware of it's orgin and the foundation for mutual exclusion between the sysFS and Perf interface can be laid out. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 29 ++++++++++++++++++++----- drivers/hwtracing/coresight/coresight-tmc-etr.c | 25 +++++++++++++++++---- drivers/hwtracing/coresight/coresight-tmc.h | 5 +++-- 3 files changed, 47 insertions(+), 12 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index e5d67e01409c..a88c76d7f473 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -108,6 +108,7 @@ static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) { + u32 val; bool allocated = false; char *buf = NULL; unsigned long flags; @@ -125,6 +126,15 @@ static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) return -EBUSY; } + val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + /* + * In sysFS mode we can have multiple writers per sink. Since this + * sink is already enabled no memory is needed and the HW need not be + * touched. + */ + if (val == CS_MODE_SYSFS) + goto out; + /* * If drvdata::buf isn't NULL, memory was allocated for a previous * trace run but wasn't read. If so simply zero-out the memory. @@ -141,9 +151,9 @@ static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) } tmc_etb_enable_hw(drvdata); - drvdata->enable = true; spin_unlock_irqrestore(&drvdata->spinlock, flags); +out: /* Free memory outside the spinlock if need be */ if (!allocated) kfree(buf); @@ -154,6 +164,7 @@ static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) static void tmc_disable_etf_sink(struct coresight_device *csdev) { + u32 val; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -163,9 +174,15 @@ static void tmc_disable_etf_sink(struct coresight_device *csdev) return; } + val = local_cmpxchg(&drvdata->mode, CS_MODE_SYSFS, CS_MODE_DISABLED); + /* Nothing to do, the TMC was already disabled */ + if (val == CS_MODE_DISABLED) + goto out; + tmc_etb_disable_hw(drvdata); tmc_etb_dump_hw(drvdata); - drvdata->enable = false; + +out: spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_info(drvdata->dev, "TMC-ETB/ETF disabled\n"); @@ -184,7 +201,7 @@ static int tmc_enable_etf_link(struct coresight_device *csdev, } tmc_etf_enable_hw(drvdata); - drvdata->enable = true; + local_set(&drvdata->mode, CS_MODE_SYSFS); spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_info(drvdata->dev, "TMC-ETF enabled\n"); @@ -204,7 +221,7 @@ static void tmc_disable_etf_link(struct coresight_device *csdev, } tmc_etf_disable_hw(drvdata); - drvdata->enable = false; + local_set(&drvdata->mode, CS_MODE_DISABLED); spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_info(drvdata->dev, "TMC disabled\n"); @@ -237,7 +254,7 @@ int tmc_read_prepare_etf(struct tmc_drvdata *drvdata) spin_lock_irqsave(&drvdata->spinlock, flags); /* The TMC isn't enabled, so there is no need to disable it */ - if (!drvdata->enable) { + if (local_read(&drvdata->mode) == CS_MODE_DISABLED) { /* * The ETB/ETF is disabled already. If drvdata::buf is NULL * trace data has been harvested. @@ -288,7 +305,7 @@ int tmc_read_unprepare_etf(struct tmc_drvdata *drvdata) } /* The TMC isn't enabled, so there is no need to enable it */ - if (!drvdata->enable) { + if (local_read(&drvdata->mode) == CS_MODE_DISABLED) { /* * The ETB/ETF is not tracing and the buffer was just read. * As such prepare to free the trace buffer. diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index c4962568276e..540d0b96a958 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -84,6 +84,7 @@ static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) { + u32 val; bool allocated = false; unsigned long flags; void __iomem *vaddr; @@ -107,6 +108,15 @@ static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) return -EBUSY; } + val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + /* + * In sysFS mode we can have multiple writers per sink. Since this + * sink is already enabled no memory is needed and the HW need not be + * touched. + */ + if (val == CS_MODE_SYSFS) + goto out; + /* * If drvdata::buf == NULL, use the memory allocated above. * Otherwise a buffer still exists from a previous session, so @@ -122,9 +132,9 @@ static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) memset(drvdata->vaddr, 0, drvdata->size); tmc_etr_enable_hw(drvdata); - drvdata->enable = true; spin_unlock_irqrestore(&drvdata->spinlock, flags); +out: /* Free memory outside the spinlock if need be */ if (!allocated) dma_free_coherent(drvdata->dev, drvdata->size, vaddr, paddr); @@ -135,6 +145,7 @@ static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) static void tmc_disable_etr_sink(struct coresight_device *csdev) { + u32 val; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -144,9 +155,15 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev) return; } + val = local_cmpxchg(&drvdata->mode, CS_MODE_SYSFS, CS_MODE_DISABLED); + /* Nothing to do, the TMC was already disabled */ + if (val == CS_MODE_DISABLED) + goto out; + tmc_etr_disable_hw(drvdata); tmc_etr_dump_hw(drvdata); - drvdata->enable = false; + +out: spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_info(drvdata->dev, "TMC-ETR disabled\n"); @@ -168,7 +185,7 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) spin_lock_irqsave(&drvdata->spinlock, flags); /* The TMC isn't enabled, so there is no need to disable it */ - if (!drvdata->enable) { + if (local_read(&drvdata->mode) == CS_MODE_DISABLED) { /* * The ETR is disabled already. If drvdata::buf is NULL * trace data has been harvested. @@ -210,7 +227,7 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata) } /* The TMC isn't enabled, so there is no need to enable it */ - if (!drvdata->enable) { + if (local_read(&drvdata->mode) == CS_MODE_DISABLED) { /* * The ETR is not tracing and trace data was just read. As * such prepare to free the trace buffer. diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 6b11caf77ad1..6dbd70861b17 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -18,6 +18,7 @@ #ifndef _CORESIGHT_TMC_H #define _CORESIGHT_TMC_H +#include #include #define TMC_RSZ 0x004 @@ -100,7 +101,7 @@ enum tmc_mem_intf_width { * @paddr: DMA start location in RAM. * @vaddr: virtual representation of @paddr. * @size: @buf size. - * @enable: this TMC is being used. + * @mode: how this TMC is being used. * @config_type: TMC variant, must be of type @tmc_config_type. * @trigger_cntr: amount of words to store after a trigger. */ @@ -116,7 +117,7 @@ struct tmc_drvdata { dma_addr_t paddr; void __iomem *vaddr; u32 size; - bool enable; + local_t mode; enum tmc_config_type config_type; u32 trigger_cntr; };