From patchwork Tue Mar 22 20:23:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 8645121 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 153BAC0553 for ; Tue, 22 Mar 2016 20:28:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EC85F2014A for ; Tue, 22 Mar 2016 20:28:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D1C8A2012D for ; Tue, 22 Mar 2016 20:28:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aiSt6-0002z9-VP; Tue, 22 Mar 2016 20:26:49 +0000 Received: from mail-io0-x22b.google.com ([2607:f8b0:4001:c06::22b]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aiSqd-00089K-CC for linux-arm-kernel@lists.infradead.org; Tue, 22 Mar 2016 20:24:17 +0000 Received: by mail-io0-x22b.google.com with SMTP id o5so171180410iod.2 for ; Tue, 22 Mar 2016 13:23:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rRBkZfuyUxLadmeVuQOAnNoV13AkaRP8ZSSckjzeMKM=; b=BeCmbjEUjOJE9UnVQVjau+DnxkXgUjabs+EtcEpa8cIIn3leXkfLZ/Icc4DiVFPdgv mSVJcs+G77qAar+MQa4tFfviecaK1K2PbHuM/xwLIunoFBdMHG/yYiZfUohoW5qUq+ap HJvDRa1a9fyaxPg1XDPM/WZC/TPlxFF7mue0A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rRBkZfuyUxLadmeVuQOAnNoV13AkaRP8ZSSckjzeMKM=; b=Fv2MmMUe7EYSgVxbSDsUYlCMH2bzKAcoUwckYOQIwsOvxb1B4SxvO+VIPBrUmCdMQY p6T8z5CeC7wSUIorR527C4LVjU5rS45X4zyoR87PlrB3T/URKuhrDHxKxqu01zA+yKQP /uADAyesL5dXHpceQhYxTGjm7eIT9nQ1hqttu9sPTIFZFIE0gek4v1fA+KMvFNY93CWp ZCw4+5ViWZPFm2LbKdtz149Uzzu/4VLhzopM8aavUO6EioQpBBlY4U+KfGCm53nU4o87 b+Onz6v92G/J8rovcBPa2Jvk1YkbIocmE1ge5nfusQH4Fe4NIEIAqW/TKk+dj5mcvJf0 +c4w== X-Gm-Message-State: AD7BkJILedFvbSJ1ik02uKQqk6vYWNAh4QUFfamudjtaeIrN3Lgcu3mNJDbh4LcV4IeHJPsN X-Received: by 10.107.18.70 with SMTP id a67mr41914658ioj.116.1458678237283; Tue, 22 Mar 2016 13:23:57 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id xo2sm8092061igb.0.2016.03.22.13.23.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Mar 2016 13:23:56 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/14] coresight: tmc: make sysFS and Perf mode mutually exclusive Date: Tue, 22 Mar 2016 14:23:18 -0600 Message-Id: <1458678202-3447-11-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1458678202-3447-1-git-send-email-mathieu.poirier@linaro.org> References: <1458678202-3447-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160322_132415_615767_85A76080 X-CRM114-Status: GOOD ( 17.49 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The sysFS and Perf access methods can't be allowed to interfere with one another. As such introducing guards to access functions that prevents moving forward if a TMC is already being used. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 76 +++++++++++++++++++++--- drivers/hwtracing/coresight/coresight-tmc-etr.c | 77 ++++++++++++++++++++++--- 2 files changed, 139 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index a88c76d7f473..c533b4494969 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -106,7 +106,7 @@ static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) +static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev, u32 mode) { u32 val; bool allocated = false; @@ -127,6 +127,12 @@ static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) } val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + /* No need to continue if already operated from Perf */ + if (val == CS_MODE_PERF) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + kfree(buf); + return -EBUSY; + } /* * In sysFS mode we can have multiple writers per sink. Since this * sink is already enabled no memory is needed and the HW need not be @@ -162,7 +168,7 @@ out: return 0; } -static void tmc_disable_etf_sink(struct coresight_device *csdev) +static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, u32 mode) { u32 val; unsigned long flags; @@ -171,16 +177,66 @@ static void tmc_disable_etf_sink(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + /* + * In Perf mode there can be only one writer per sink. There + * is also no need to continue if the ETB/ETR is already operated + * from sysFS. + */ + if (val != CS_MODE_DISABLED) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + tmc_etb_enable_hw(drvdata); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return 0; +} + +static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) +{ + switch (mode) { + case CS_MODE_SYSFS: + return tmc_enable_etf_sink_sysfs(csdev, mode); + case CS_MODE_PERF: + return tmc_enable_etf_sink_perf(csdev, mode); + } + + /* We shouldn't be here */ + return -EINVAL; +} + +static void tmc_disable_etf_sink(struct coresight_device *csdev) +{ + u32 mode; + unsigned long flags; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); return; } - val = local_cmpxchg(&drvdata->mode, CS_MODE_SYSFS, CS_MODE_DISABLED); - /* Nothing to do, the TMC was already disabled */ - if (val == CS_MODE_DISABLED) + mode = local_xchg(&drvdata->mode, CS_MODE_DISABLED); + /* Nothing to do, the ETB/ETF was already disabled */ + if (mode == CS_MODE_DISABLED) goto out; + /* The engine has to be stopped in both sysFS and Perf mode */ tmc_etb_disable_hw(drvdata); - tmc_etb_dump_hw(drvdata); + + /* + * If we operated from sysFS, dump the trace data for retrieval + * via /dev/. From Perf trace data is handled via the Perf ring + * buffer. + */ + if (mode == CS_MODE_SYSFS) + tmc_etb_dump_hw(drvdata); out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -253,7 +309,13 @@ int tmc_read_prepare_etf(struct tmc_drvdata *drvdata) spin_lock_irqsave(&drvdata->spinlock, flags); - /* The TMC isn't enabled, so there is no need to disable it */ + /* Don't interfere if operated from Perf */ + if (local_read(&drvdata->mode) == CS_MODE_PERF) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + /* The ETB/ETF isn't enabled, so there is no need to disable it */ if (local_read(&drvdata->mode) == CS_MODE_DISABLED) { /* * The ETB/ETF is disabled already. If drvdata::buf is NULL diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 540d0b96a958..50a2e0a83714 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -82,7 +82,7 @@ static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) +static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev, u32 mode) { u32 val; bool allocated = false; @@ -109,6 +109,13 @@ static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) } val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + /* No need to continue if already operated from Perf */ + if (val == CS_MODE_PERF) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + dma_free_coherent(drvdata->dev, drvdata->size, vaddr, paddr); + return -EBUSY; + } + /* * In sysFS mode we can have multiple writers per sink. Since this * sink is already enabled no memory is needed and the HW need not be @@ -143,7 +150,7 @@ out: return 0; } -static void tmc_disable_etr_sink(struct coresight_device *csdev) +static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, u32 mode) { u32 val; unsigned long flags; @@ -152,16 +159,66 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + /* + * In Perf mode there can be only one writer per sink. There + * is also no need to continue if the ETR is already operated + * from sysFS. + */ + if (val != CS_MODE_DISABLED) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + tmc_etr_enable_hw(drvdata); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return 0; +} + +static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) +{ + switch (mode) { + case CS_MODE_SYSFS: + return tmc_enable_etr_sink_sysfs(csdev, mode); + case CS_MODE_PERF: + return tmc_enable_etr_sink_perf(csdev, mode); + } + + /* We shouldn't be here */ + return -EINVAL; +} + +static void tmc_disable_etr_sink(struct coresight_device *csdev) +{ + u32 mode; + unsigned long flags; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); return; } - val = local_cmpxchg(&drvdata->mode, CS_MODE_SYSFS, CS_MODE_DISABLED); - /* Nothing to do, the TMC was already disabled */ - if (val == CS_MODE_DISABLED) + mode = local_xchg(&drvdata->mode, CS_MODE_DISABLED); + /* Nothing to do, the ETR was already disabled */ + if (mode == CS_MODE_DISABLED) goto out; + /* The engine has to be stopped in both sysFS and Perf mode */ tmc_etr_disable_hw(drvdata); - tmc_etr_dump_hw(drvdata); + + /* + * If we operated from sysFS, dump the trace data for retrieval + * via /dev/. From Perf trace data is handled via the Perf ring + * buffer. + */ + if (mode == CS_MODE_SYSFS) + tmc_etr_dump_hw(drvdata); out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -184,7 +241,13 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) spin_lock_irqsave(&drvdata->spinlock, flags); - /* The TMC isn't enabled, so there is no need to disable it */ + /* Don't interfere if operated from Perf */ + if (local_read(&drvdata->mode) == CS_MODE_PERF) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + /* The ETR isn't enabled, so there is no need to disable it */ if (local_read(&drvdata->mode) == CS_MODE_DISABLED) { /* * The ETR is disabled already. If drvdata::buf is NULL