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[92.17.247.99]) by smtp.gmail.com with ESMTPSA id w125sm4436108wmw.18.2016.03.23.12.47.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 23 Mar 2016 12:47:18 -0700 (PDT) From: Srinivas Kandagatla To: Andy Gross , linux-arm-msm@vger.kernel.org Subject: [PATCH 03/12] ARM: dts: apq8064: add gsbi7 i2c support Date: Wed, 23 Mar 2016 19:47:16 +0000 Message-Id: <1458762436-9446-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1458762366-9233-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1458762366-9233-1-git-send-email-srinivas.kandagatla@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160323_124741_220132_0883A758 X-CRM114-Status: GOOD ( 10.75 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Srinivas Kandagatla , linux-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support to gsbi7 i2c which is used in some of the new boards. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 25 +++++++++++++++++++++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 13 +++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi index 8bb5e5f..4102a98 100644 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi @@ -219,4 +219,29 @@ function = "gsbi7"; }; }; + + i2c7_pins: i2c7 { + mux { + pins = "gpio84", "gpio85"; + function = "gsbi7"; + }; + + pinconf { + pins = "gpio84", "gpio85"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c7_pins_sleep: i2c7_pins_sleep { + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + pinconf { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 81b4290..f064f59 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -417,6 +417,19 @@ clock-names = "core", "iface"; status = "disabled"; }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + pinctrl-0 = <&i2c7_pins>; + pinctrl-1 = <&i2c7_pins_sleep>; + pinctrl-names = "default", "sleep"; + reg = <0x16680000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI7_QUP_CLK>, + <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; }; rng@1a500000 {