From patchwork Wed Mar 30 16:14:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris BREZILLON X-Patchwork-Id: 8700801 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2D3B2C0553 for ; Wed, 30 Mar 2016 16:42:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1F26320382 for ; Wed, 30 Mar 2016 16:42:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 267B020221 for ; Wed, 30 Mar 2016 16:42:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1alJBT-00032b-O7; Wed, 30 Mar 2016 16:41:31 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1alImm-000818-QN; Wed, 30 Mar 2016 16:16:06 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 095851861; Wed, 30 Mar 2016 18:15:37 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (LMontsouris-657-1-184-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 8E0451828; Wed, 30 Mar 2016 18:15:23 +0200 (CEST) From: Boris Brezillon To: David Woodhouse , Brian Norris , linux-mtd@lists.infradead.org, Boris Brezillon , Richard Weinberger Subject: [PATCH v5 21/50] mtd: nand: jz4740: switch to mtd_ooblayout_ops Date: Wed, 30 Mar 2016 18:14:36 +0200 Message-Id: <1459354505-32551-22-git-send-email-boris.brezillon@free-electrons.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1459354505-32551-1-git-send-email-boris.brezillon@free-electrons.com> References: <1459354505-32551-1-git-send-email-boris.brezillon@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160330_091601_353112_F8B233EA X-CRM114-Status: GOOD ( 21.04 ) X-Spam-Score: -2.9 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-mips@linux-mips.org, Krzysztof Kozlowski , Harvey Hunt , Nicolas Ferre , Stefan Agner , linux-sunxi@googlegroups.com, Alexandre Belloni , punnaiah choudary kalluri , Robert Jarzmik , devel@driverdev.osuosl.org, Archit Taneja , linux-samsung-soc@vger.kernel.org, Kamal Dasu , Josh Wu , Chen-Yu Tsai , Kukjin Kim , bcm-kernel-feedback-list@broadcom.com, Ezequiel Garcia , Huang Shijie , Jean-Christophe Plagniol-Villard , Haojian Zhuang , Han Xu , linux-arm-kernel@lists.infradead.org, Priit Laes , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Ralf Baechle , Wenyou Yang , Kyungmin Park , linux-api@vger.kernel.org, Maxime Ripard , Daniel Mack MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Implementing the mtd_ooblayout_ops interface is the new way of exposing ECC/OOB layout to MTD users. Signed-off-by: Boris Brezillon Acked-by: Lars-Peter Clausen --- arch/mips/include/asm/mach-jz4740/jz4740_nand.h | 2 +- arch/mips/jz4740/board-qi_lb60.c | 87 +++++++++++++++---------- drivers/mtd/nand/jz4740_nand.c | 2 +- 3 files changed, 53 insertions(+), 38 deletions(-) diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h index 398733e..7f7b0fc 100644 --- a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h +++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h @@ -27,7 +27,7 @@ struct jz_nand_platform_data { unsigned char banks[JZ_NAND_NUM_BANKS]; - void (*ident_callback)(struct platform_device *, struct nand_chip *, + void (*ident_callback)(struct platform_device *, struct mtd_info *, struct mtd_partition **, int *num_partitions); }; diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 934b15b..a1c1afb 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -50,20 +50,6 @@ static bool is_avt2; #define QI_LB60_GPIO_KEYIN8 JZ_GPIO_PORTD(26) /* NAND */ -static struct nand_ecclayout qi_lb60_ecclayout_1gb = { - .eccbytes = 36, - .eccpos = { - 6, 7, 8, 9, 10, 11, 12, 13, - 14, 15, 16, 17, 18, 19, 20, 21, - 22, 23, 24, 25, 26, 27, 28, 29, - 30, 31, 32, 33, 34, 35, 36, 37, - 38, 39, 40, 41 - }, - .oobfree = { - { .offset = 2, .length = 4 }, - { .offset = 42, .length = 22 } - }, -}; /* Early prototypes of the QI LB60 had only 1GB of NAND. * In order to support these devices as well the partition and ecc layout is @@ -86,25 +72,6 @@ static struct mtd_partition qi_lb60_partitions_1gb[] = { }, }; -static struct nand_ecclayout qi_lb60_ecclayout_2gb = { - .eccbytes = 72, - .eccpos = { - 12, 13, 14, 15, 16, 17, 18, 19, - 20, 21, 22, 23, 24, 25, 26, 27, - 28, 29, 30, 31, 32, 33, 34, 35, - 36, 37, 38, 39, 40, 41, 42, 43, - 44, 45, 46, 47, 48, 49, 50, 51, - 52, 53, 54, 55, 56, 57, 58, 59, - 60, 61, 62, 63, 64, 65, 66, 67, - 68, 69, 70, 71, 72, 73, 74, 75, - 76, 77, 78, 79, 80, 81, 82, 83 - }, - .oobfree = { - { .offset = 2, .length = 10 }, - { .offset = 84, .length = 44 }, - }, -}; - static struct mtd_partition qi_lb60_partitions_2gb[] = { { .name = "NAND BOOT partition", @@ -123,19 +90,67 @@ static struct mtd_partition qi_lb60_partitions_2gb[] = { }, }; +static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + if (section) + return -ERANGE; + + oobregion->length = 36; + oobregion->offset = 6; + + if (mtd->oobsize == 128) { + oobregion->length *= 2; + oobregion->offset *= 2; + } + + return 0; +} + +static int qi_lb60_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + int eccbytes = 36, eccoff = 6; + + if (section > 1) + return -ERANGE; + + if (mtd->oobsize == 128) { + eccbytes *= 2; + eccoff *= 2; + } + + if (!section) { + oobregion->offset = 2; + oobregion->length = eccoff - 2; + } else { + oobregion->offset = eccoff + eccbytes; + oobregion->length = mtd->oobsize - oobregion->offset; + } + + return 0; +} + +static const struct mtd_ooblayout_ops qi_lb60_ooblayout_ops = { + .ecc = qi_lb60_ooblayout_ecc, + .free = qi_lb60_ooblayout_free, +}; + static void qi_lb60_nand_ident(struct platform_device *pdev, - struct nand_chip *chip, struct mtd_partition **partitions, + struct mtd_info *mtd, struct mtd_partition **partitions, int *num_partitions) { + struct nand_chip *chip = mtd_to_nand(mtd); + if (chip->page_shift == 12) { - chip->ecc.layout = &qi_lb60_ecclayout_2gb; *partitions = qi_lb60_partitions_2gb; *num_partitions = ARRAY_SIZE(qi_lb60_partitions_2gb); } else { - chip->ecc.layout = &qi_lb60_ecclayout_1gb; *partitions = qi_lb60_partitions_1gb; *num_partitions = ARRAY_SIZE(qi_lb60_partitions_1gb); } + + mtd_set_ooblayout(mtd, &qi_lb60_ooblayout_ops); } static struct jz_nand_platform_data qi_lb60_nand_pdata = { diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c index 673ceb2..df74408 100644 --- a/drivers/mtd/nand/jz4740_nand.c +++ b/drivers/mtd/nand/jz4740_nand.c @@ -476,7 +476,7 @@ static int jz_nand_probe(struct platform_device *pdev) } if (pdata && pdata->ident_callback) { - pdata->ident_callback(pdev, chip, &pdata->partitions, + pdata->ident_callback(pdev, mtd, &pdata->partitions, &pdata->num_partitions); }