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Thu, 31 Mar 2016 11:48:09 +0900 (KST) From: Chanwoo Choi To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Subject: [PATCH v4 2/9] dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250 Date: Thu, 31 Mar 2016 11:47:58 +0900 Message-id: <1459392485-11327-3-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1459392485-11327-1-git-send-email-cw00.choi@samsung.com> References: <1459392485-11327-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRmVeSWpSXmKPExsWyRsSkQPdl/58wgynPrS22H3nGanH9y3NW i/lHzrFaTLo/gcXixq82VovXLwwt+h+/ZrbY9Pgaq8XlXXPYLGac38dksWjrF3aLw2/aWS1m TH7JZrFq1x9GBz6PnbPusntsWtXJ5rF5Sb1H35ZVjB6fN8kFsEZx2aSk5mSWpRbp2yVwZbyZ vpK1oIOn4sqRu+wNjAc4uxg5OSQETCSutW1hhbDFJC7cW8/WxcjFISSwglFi59w25i5GDrCi PXtjQGqEBGYxSnzYHwJhf2GU6LzlCWKzCWhJ7H9xgw3EFhGIk5h4EcJmFpjFJDFvfiGILSwQ IbH1xzmwOIuAqkT36Q6wvbwCrhLr125jhLhBTuLDnkfsIDangJvEvRWX2SF2uUqsmTmHGeQ2 CYFT7BLLf81lhBgkIPFt8iEWiDtlJTYdYIaYIylxcMUNlgmMwgsYGVYxiqYWJBcUJ6UXGekV J+YWl+al6yXn525iBEbJ6X/P+nYw3jxgfYhRgINRiYdXI+1PmBBrYllxZe4hRlOgDROZpUST 84GxmFcSb2hsZmRhamJqbGRuaaYkzpsg9TNYSCA9sSQ1OzW1ILUovqg0J7X4ECMTB6dUA+Ns fW930Zccbg/4W34fbK0L1NyzTeuWDVfuS5tvu//v8l62pWJXhfGDgkwJaeGUy3MSjsz7VP2p +du91QYPqzsfPSxxtwpn5fn79pt0qrbjGas5boL+c4y6hNOqi7dsbyw5vP59z/HnWwz6n96P OqnKevvVbofv528uKhecIRgV/LLs4tOvLoVKLMUZiYZazEXFiQBqOKjAjQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOIsWRmVeSWpSXmKPExsVy+t9jQd2X/X/CDG7fNLPYfuQZq8X1L89Z LeYfOcdqMen+BBaLG7/aWC1evzC06H/8mtli0+NrrBaXd81hs5hxfh+TxaKtX9gtDr9pZ7WY Mfklm8WqXX8YHfg8ds66y+6xaVUnm8fmJfUefVtWMXp83iQXwBrVwGiTkZqYklqkkJqXnJ+S mZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA3SokkJZYk4pUCggsbhYSd8O04TQ EDddC5jGCF3fkCC4HiMDNJCwhjHjzfSVrAUdPBVXjtxlb2A8wNnFyMEhIWAisWdvTBcjJ5Ap JnHh3no2EFtIYBajxIf9IRD2F0aJzlueIDabgJbE/hc3wGpEBOIkJl6EsJkFZjFJzJtfCGIL C0RIbP1xDizOIqAq0X26gxXE5hVwlVi/dhsjxC45iQ97HrGD2JwCbhL3Vlxmh9jlKrFm5hzm CYy8CxgZVjFKpBYkFxQnpeca5aWW6xUn5haX5qXrJefnbmIER+Iz6R2Mh3e5H2IU4GBU4uG9 kPwnTIg1say4MvcQowQHs5IIb2gfUIg3JbGyKrUoP76oNCe1+BCjKdBhE5mlRJPzgUkiryTe 0NjEzMjSyNzQwsjYXEmc9/H/dWFCAumJJanZqakFqUUwfUwcnFINjP27TAT3223w2SNVbHe1 xyqi5NSOe6ztzk9ePiw4k9MoveZgZ93Wo99Tv964tvma5WJfPZbIv5XBMyruf7h5Ncn+1J8/ +oufPt9RfHs+w67DE7u8zdU39ai49a2vVvzwpLhQO2zFmvmrOGeV11x53qN77OP5kgUTD522 9jqp5eczny/C6J7O1GdKLMUZiYZazEXFiQDGzb4D2gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160330_194838_373402_F88253B9 X-CRM114-Status: GOOD ( 10.56 ) X-Spam-Score: -7.9 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: inki.dae@samsung.com, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, pankaj.dubey@samsung.com, sw0312.kim@samsung.com, linux-kernel@vger.kernel.org, andi.shyti@samsung.com, jh80.chung@samsung.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the new clock id for both UART2 and MM2 device for Exynos3250 SoC. Signed-off-by: Chanwoo Choi --- include/dt-bindings/clock/exynos3250.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index 63d01c15d2b3..c796ff02ceeb 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -79,6 +79,8 @@ #define CLK_MOUT_CORE 58 #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 +#define CLK_MOUT_UART2 61 +#define CLK_MOUT_MMC2 62 /* Dividers */ #define CLK_DIV_GPL 64 @@ -127,6 +129,9 @@ #define CLK_DIV_CORE 107 #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 +#define CLK_DIV_UART2 110 +#define CLK_DIV_MMC2_PRE 111 +#define CLK_DIV_MMC2 112 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -223,6 +228,8 @@ #define CLK_BLOCK_MFC 219 #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 +#define CLK_UART2 222 +#define CLK_SDMMC2 223 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -249,12 +256,14 @@ #define CLK_SCLK_SPI0 245 #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 +#define CLK_SCLK_UART2 248 +#define CLK_SCLK_MMC2 249 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 248 +#define CLK_NR_CLKS 250 /* * CMU DMC