From patchwork Mon Apr 4 14:52:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 8741581 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C14129F39A for ; Mon, 4 Apr 2016 14:55:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D64C720270 for ; Mon, 4 Apr 2016 14:55:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 863CB2028D for ; Mon, 4 Apr 2016 14:55:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1an5tK-0005pj-5z; Mon, 04 Apr 2016 14:54:10 +0000 Received: from mail-lf0-x236.google.com ([2a00:1450:4010:c07::236]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1an5sG-00057D-VO for linux-arm-kernel@lists.infradead.org; Mon, 04 Apr 2016 14:53:07 +0000 Received: by mail-lf0-x236.google.com with SMTP id g184so100024814lfb.3 for ; Mon, 04 Apr 2016 07:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cfFGiCbxBgMgsD6JKR+fjcPMOSP0PJ7bugSSUQ+I94k=; b=TZSXy0UD1KJPByNux7oKewSA9/DxWJoSZG2Hhduqj1uLh+u+28GWRAe6GXkB38NGet dGq3puqbwZtWTswZi216K+49biJ79Dl83mcNd3hzKwZy/VspLlumRTksMqYSYPEXj5Oj ga1/dAyq4ov2GQc2ZKxLxupJg55KtOCwlx1bQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cfFGiCbxBgMgsD6JKR+fjcPMOSP0PJ7bugSSUQ+I94k=; b=LuGgn3sqIihwGLNvr3kFICOMvOEiksDtYvGqSKWfs/s/F55icf1t1edccngMJOznsp +11OImyXLfQlbqZQifduIPPZvrXfWP7EOVNAwSSE8xWQUyTfStiM2CtK2qh+IuUAjB+R 0IFDCMidPhWSX6y9r95c+1mk+iAO6BmvIhPE4/fN/of9/UWBcuArpOBSYb7wZ5UNCwbC rOb52yJznrQJDTZVUxjq1oEUALo6qDaIcERS3jpu0+3FvZToiqRgqQ0IgjLxDCFEQYMj FQPCqhIQWlRoAsd3b8pEImJzyZgc0MClOZ941gsEHv/v0+0eF9YEyoBVg5F28Zdihn6U oo9w== X-Gm-Message-State: AD7BkJJFPqnl5hlVLf3NtnbM407oZxXtsUpnDhhKSa4PFj9sZQkMA2vrRZ+yNV9CI3D87P2u X-Received: by 10.28.186.196 with SMTP id k187mr12463415wmf.17.1459781562731; Mon, 04 Apr 2016 07:52:42 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id cf6sm7922528wjc.12.2016.04.04.07.52.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 04 Apr 2016 07:52:41 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, will.deacon@arm.com, catalin.marinas@arm.com, mark.rutland@arm.com Subject: [PATCH 7/8] arm64/kernel: drop __PHYS_OFFSET register with file scope from head.S Date: Mon, 4 Apr 2016 16:52:23 +0200 Message-Id: <1459781544-14310-8-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1459781544-14310-1-git-send-email-ard.biesheuvel@linaro.org> References: <1459781544-14310-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160404_075305_374834_908BD53A X-CRM114-Status: GOOD ( 11.38 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Instead of keeping __PHYS_OFFSET in a callee saved register with file scope in head.S, derive the value on demand. This makes for cleaner and more maintainable code. Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 26 +++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index d28fc345bec3..23d03da7ecfe 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -213,7 +213,6 @@ ENTRY(stext) bl preserve_boot_args bl el2_setup // Drop to EL1, w0=cpu_boot_mode mov x23, xzr // KASLR offset, defaults to 0 - adrp x24, __PHYS_OFFSET bl set_cpu_boot_mode_flag bl __create_page_tables /* @@ -396,7 +395,7 @@ __create_page_tables: create_pgd_entry x0, x5, x3, x6 ldr w6, kernel_img_size add x6, x6, x5 - mov x3, x24 // phys offset + adrp x3, __PHYS_OFFSET create_block_map x0, x7, x3, x5, x6 /* @@ -417,7 +416,7 @@ kernel_img_size: .ltorg /* - * The following fragment of code is executed with the MMU enabled. + * __mmap_switched(u64 phys_offset) - virtual entry point for the boot CPU */ __mmap_switched: adrp x4, init_thread_union @@ -431,14 +430,6 @@ __mmap_switched: msr vbar_el1, x8 // vector table address isb - // Clear BSS - adr_l x0, __bss_start - mov x1, xzr - adr_l x2, __bss_stop - sub x2, x2, x0 - bl __pi_memset - dsb ishst // Make zero page visible to PTW - #ifdef CONFIG_RELOCATABLE /* @@ -479,8 +470,17 @@ __mmap_switched: #endif ldr_l x4, kimage_vaddr // Save the offset between - sub x4, x4, x24 // the kernel virtual and + sub x4, x4, x0 // the kernel virtual and str_l x4, kimage_voffset, x5 // physical mappings + + // Clear BSS + adr_l x0, __bss_start + mov x1, xzr + adr_l x2, __bss_stop + sub x2, x2, x0 + bl __pi_memset + dsb ishst // Make zero page visible to PTW + #ifdef CONFIG_KASAN bl kasan_early_init #endif @@ -774,6 +774,7 @@ __enable_mmu: mov x20, x1 // preserve branch target #ifdef CONFIG_RANDOMIZE_BASE mov x19, x0 // preserve new SCTLR_EL1 value + adrp x0, __PHYS_OFFSET blr x1 /* @@ -792,6 +793,7 @@ __enable_mmu: isb add x20, x20, x23 // relocated __mmap_switched #endif + adrp x0, __PHYS_OFFSET br x20 ENDPROC(__enable_mmu)