From patchwork Mon Apr 4 16:22:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 8742281 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A374AC0553 for ; Mon, 4 Apr 2016 16:25:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B8BD22024F for ; Mon, 4 Apr 2016 16:25:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB24C201FA for ; Mon, 4 Apr 2016 16:25:17 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1an7I4-00067h-Oc; Mon, 04 Apr 2016 16:23:48 +0000 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76] helo=wens.csie.org) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1an7HV-0005oV-Hb for linux-arm-kernel@lists.infradead.org; Mon, 04 Apr 2016 16:23:15 +0000 Received: by wens.csie.org (Postfix, from userid 1000) id D2D935F8FA; Tue, 5 Apr 2016 00:22:47 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Florian Fainelli , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Subject: [PATCH RFC 1/5] net: phy: sun8i-h3-ephy: Add bindings for Allwinner H3 Ethernet PHY Date: Tue, 5 Apr 2016 00:22:30 +0800 Message-Id: <1459786954-12649-2-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1459786954-12649-1-git-send-email-wens@csie.org> References: <1459786954-12649-1-git-send-email-wens@csie.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160404_092313_797157_38A7F0A4 X-CRM114-Status: GOOD ( 12.39 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai , LABBE Corentin , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and configured through a memory mapped hardware register. This same register also configures the MAC interface mode and TX clock source. Also covered by the register, but not supported in these bindings, are TX/RX clock delay chains and inverters, and an RMII module. Signed-off-by: Chen-Yu Tsai Acked-by: Rob Herring --- .../bindings/net/allwinner,sun8i-h3-ephy.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt b/Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt new file mode 100644 index 000000000000..146f227e6d88 --- /dev/null +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt @@ -0,0 +1,44 @@ +* Allwinner H3 E(thernet) PHY + +The Allwinner H3 integrates an MII ethernet PHY. As with external PHYs, +before it can be configured over the MDIO bus and used, certain hardware +features must be configured, such as the PHY address and LED polarity. +The PHY must also be powered on and brought out of reset. + +This is accomplished with regulators and pull-up/downs for external PHYs. +For this internal PHY, a hardware register is programmed. + +The same hardware register also contains clock and interface controls +for the MAC. This is also present in earlier SoCs, and is covered by +"allwinner,sun7i-a20-gmac-clk". The controls in the H3 are slightly +different due to the inclusion of what appears to be an RMII-MII +bridge. + +Required properties: +- compatible: should be "allwinner,sun8i-h3-ephy" +- reg: address and length of the register set for the device +- clocks: A phandle to the reference clock for this device +- resets: A phandle to the reset control for this device + +Ethernet PHY related properties: +- allwinner,ephy-addr: the MDIO bus address the PHY should respond to. + If this is not set, the external PHY is used, and + everything else in this section is ignored. +- allwinner,leds-active-low: LEDs are active low. Without this, LEDs are + active high. + +Ethernet MAC clock related properties: +- #clock-cells: should be 0 +- clock-output-names: "mac_tx" + +Example: + +ethernet-phy@01c00030 { + compatible = "allwinner,sun8i-h3-ephy"; + reg = <0x01c00030 0x4>; + clocks = <&bus_gates 128>; + resets = <&ahb_rst 66>; + allwinner,ephy-addr = <0x1>; + #clock-cells = <0>; + clock-output-names = "mac_tx"; +};