From patchwork Mon Apr 11 23:29:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Daney X-Patchwork-Id: 8806211 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9A2109F3D1 for ; Mon, 11 Apr 2016 23:31:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A967F20219 for ; Mon, 11 Apr 2016 23:31:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B85E5201F2 for ; Mon, 11 Apr 2016 23:31:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aplHP-0004qJ-Ni; Mon, 11 Apr 2016 23:30:03 +0000 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aplHM-0004Uc-25 for linux-arm-kernel@lists.infradead.org; Mon, 11 Apr 2016 23:30:01 +0000 Received: by mail-pa0-x22f.google.com with SMTP id zm5so1120211pac.0 for ; Mon, 11 Apr 2016 16:29:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=fnCdKlrMlrjky5vQvM++JTvn92Rz5UzkLALIUNlq+Do=; b=rBT+bTidB+erPbhIHsejJ/6OcYHK7KnKOcN7iVBMJC1nuUfb5B5Gxn6PzeuKT/uv5j w93P3kyAxGPrWTOD1SX2cSqMQryeFoQWZlQ1n9uDfiOBdhnlNK/jH2Ysrw/XYZnLMeex 1Yd447anXo0yh+zYff+eLYkLVtcAm0RzY2wOUJYtRkeDNZsP//KTdvND9OzmWGC+8JVR UJLcgDvGdj/bmf6JPvDoJJ3PVP83A0srV2MdJ02H1V4JBKZIRvmohuIF57Wv5zsqX2Ka fXAG/lzz5Nhcbx/ATdLrfV2uL9sL8i1JsgzMjduDLRk6TwwY5V+9deWDqwMN+oAc2rKx 0jlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=fnCdKlrMlrjky5vQvM++JTvn92Rz5UzkLALIUNlq+Do=; b=GAY+cLAR3RfPI622GUtTBoow1X8E6Re/CyToW+S+m8KM57Y6XVdIMkOkeG2GPTLkPo pGQ1pa7MSUCad7FopUXdpVAUI4nYOZ84P5aLXCbtYv1aiC7pe85X8ZmtMRFQQtej+bBU EeW0nLw9aHRvtGJudoI7O1+d/jHQ5a4zq7oJKQNBrCFjSvtQ4kX7M6ZwIoUoJONSEsjR 9ONxvMqdDEaTQL6/0QwqROsRp1SwEeCH2vhHdsyANkow4NSaZMFBfGpz6zAqMzXDaQRi qwDJgEHqPNVB5WIhsh5AwzUX4iTNvae4oWIiWjSe4wnDnOZeDoCUmrQUgFoLxy5NDdVN AlUQ== X-Gm-Message-State: AOPr4FX7lvDT3DLBTWGi8vxcs2qee2XShhHRIXZfUhDETuw3wDNkFuGs9bh6pLBFHzZvAQ== X-Received: by 10.66.65.133 with SMTP id x5mr182868pas.108.1460417377825; Mon, 11 Apr 2016 16:29:37 -0700 (PDT) Received: from dl.caveonetworks.com ([64.2.3.194]) by smtp.gmail.com with ESMTPSA id s26sm38583419pfa.0.2016.04.11.16.29.35 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 11 Apr 2016 16:29:35 -0700 (PDT) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id u3BNTYdJ013181; Mon, 11 Apr 2016 16:29:34 -0700 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id u3BNTXPi013180; Mon, 11 Apr 2016 16:29:33 -0700 From: David Daney To: Bjorn Helgaas , linux-pci@vger.kernel.org Subject: [PATCH] pci, pci-thunder-pem: Don't clobber read-only bits in bridge config registers. Date: Mon, 11 Apr 2016 16:29:32 -0700 Message-Id: <1460417372-13147-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160411_163000_176802_FC7B2615 X-CRM114-Status: GOOD ( 15.89 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, David Daney MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: David Daney The 32-bit addressing modes in the I/O and Prefetchable Memory registers are required to be read-only. Since the underlying access method allows them to be set, we must emulate their read-only nature and always set them. Signed-off-by: David Daney --- drivers/pci/host/pci-thunder-pem.c | 42 ++++++++++++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/pci/host/pci-thunder-pem.c b/drivers/pci/host/pci-thunder-pem.c index cabb92a..196adf6 100644 --- a/drivers/pci/host/pci-thunder-pem.c +++ b/drivers/pci/host/pci-thunder-pem.c @@ -153,11 +153,11 @@ static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn, * reserved bits, this makes the code simpler and is OK as the bits * are not affected by writing zeros to them. */ -static u32 thunder_pem_bridge_w1c_bits(int where) +static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned) { u32 w1c_bits = 0; - switch (where & ~3) { + switch (where_aligned) { case 0x04: /* Command/Status */ case 0x1c: /* Base and I/O Limit/Secondary Status */ w1c_bits = 0xff000000; @@ -184,12 +184,34 @@ static u32 thunder_pem_bridge_w1c_bits(int where) return w1c_bits; } +/* Some bits must be written to one so they appear to be read-only. */ +static u32 thunder_pem_bridge_w1_bits(u64 where_aligned) +{ + u32 w1_bits; + + switch (where_aligned) { + case 0x1c: /* I/O Base / I/O Limit, Secondary Status*/ + /* Force 32-bit I/O addressing. */ + w1_bits = 0x0101; + break; + case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */ + /* Force 64-bit addressing */ + w1_bits = 0x00010001; + break; + default: + w1_bits = 0; + break; + } + return w1_bits; +} + static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { struct gen_pci *pci = bus->sysdata; struct thunder_pem_pci *pem_pci; u64 write_val, read_val; + u64 where_aligned = where & ~3ull; u32 mask = 0; pem_pci = container_of(pci, struct thunder_pem_pci, gen_pci); @@ -205,8 +227,7 @@ static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn, */ switch (size) { case 1: - read_val = where & ~3ull; - writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD); + writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD); read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD); read_val >>= 32; mask = ~(0xff << (8 * (where & 3))); @@ -215,8 +236,7 @@ static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn, val |= (u32)read_val; break; case 2: - read_val = where & ~3ull; - writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD); + writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD); read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD); read_val >>= 32; mask = ~(0xffff << (8 * (where & 3))); @@ -244,11 +264,17 @@ static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn, } /* + * Some bits must be read-only with value of one. Since the + * access method allows these to be cleared if a zero is + * written, force them to one before writing. + */ + val |= thunder_pem_bridge_w1_bits(where_aligned); + + /* * Low order bits are the config address, the high order 32 * bits are the data to be written. */ - write_val = where & ~3ull; - write_val |= (((u64)val) << 32); + write_val = (((u64)val) << 32) | where_aligned; writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR); return PCIBIOS_SUCCESSFUL; }