From patchwork Tue Apr 12 17:54:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 8813561 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 57C289F39A for ; Tue, 12 Apr 2016 18:03:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9D5B120320 for ; Tue, 12 Apr 2016 18:03:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 959EB201FE for ; Tue, 12 Apr 2016 18:03:19 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aq2co-0004wJ-Ph; Tue, 12 Apr 2016 18:01:18 +0000 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aq2XM-0007G7-PA for linux-arm-kernel@lists.infradead.org; Tue, 12 Apr 2016 17:55:45 +0000 Received: by mail-pa0-x22f.google.com with SMTP id zm5so17525207pac.0 for ; Tue, 12 Apr 2016 10:55:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qScI/pIGeZU7RxuVHw1igKjtXw1LtNinEVYKNjU1OlA=; b=gAxCN1L0nzhhFiu2Fc58wD1JZ2gqMNYu2p3C38DpARUEZ8n10wFPdPXKCX6j5TNGzw tPzXN0akaddvxTq9xABVa0mqWvieipvWtKOWc1pGbxI/XVrBOh8jK9wB3zftSVxyna18 ccXGCfEP3flcBIXIA/T2Mknjv/KhYiN0zmmdM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qScI/pIGeZU7RxuVHw1igKjtXw1LtNinEVYKNjU1OlA=; b=gTfz5iSZdFkpkupA9BiO4/LJMEW43iL/QUoc19pVzHdSLiy+etE4sCsn4rqUjjqFEt XBcx3ouw73ZHt4CG3OKqXKJgUH31oixy2YhngOYs0Lchp+zLqZuYPEtRk3KEaHYJ3UsQ dKvbVGm8csua+AwhKKNaEaWuET3ljoYuS25OTGQ9bIl70D+e6WzAErV1hyYSZbM48sll LnmAFNViouGI1KQly1RzX96s7vL6AMIM+g93JAXVV/UNyMWuFp+F1eaXjRzO1vfJAYnU is4vSCHEv1xCOGQondRhWA7PARq+dVcAaJKtJnC77orZ6s0oK/kLQD4g5ttgI1IlMAzT f2dQ== X-Gm-Message-State: AOPr4FWi2Vr6u2g30+/PLhfs1CTBLKLNazy0SGQqI5hnHLxOlhnz1SAqf4razMbhvCEeT4VH X-Received: by 10.66.229.1 with SMTP id sm1mr4378603pac.26.1460483720265; Tue, 12 Apr 2016 10:55:20 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id p189sm24633204pfb.51.2016.04.12.10.55.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Apr 2016 10:55:19 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org, Suzuki.Poulose@arm.com Subject: [PATCH V2 14/15] coresight: tmc: implementing TMC-ETR AUX space API Date: Tue, 12 Apr 2016 11:54:51 -0600 Message-Id: <1460483692-25061-15-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1460483692-25061-1-git-send-email-mathieu.poirier@linaro.org> References: <1460483692-25061-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160412_105540_994820_83926ED3 X-CRM114-Status: GOOD ( 22.55 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch implement the AUX area interfaces required to use the TMC (configured as an ETR) from the Perf sub-system. The heuristic is heavily borrowed from the ETB10 and TMC-ETF implementation. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 6 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 142 ++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 3 + 3 files changed, 148 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index fff175d4020d..6a449e2ddf5f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -378,9 +378,9 @@ static unsigned long tmc_reset_etf_buffer(struct coresight_device *csdev, return size; } -static void tmc_update_etf_buffer(struct coresight_device *csdev, - struct perf_output_handle *handle, - void *sink_config) +void tmc_update_etf_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config) { int i, cur; u32 *buf_ptr; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 04fc63d85696..bf12a6854a5f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -15,11 +15,30 @@ * this program. If not, see . */ +#include #include #include +#include + #include "coresight-priv.h" #include "coresight-tmc.h" +/** + * struct cs_etr_buffer - keep track of a recording session' specifics + * @tmc: generic portion of the TMC buffers + * @paddr: the physical address of a DMA'able contiguous memory area + * @vaddr: the virtual address associated to @paddr + * @size: how much memory we have, starting at @paddr + * @dev: the device @vaddr has been tied to + */ +struct cs_etr_buffers { + struct cs_tmc_buffers tmc; + dma_addr_t paddr; + void __iomem *vaddr; + u32 size; + struct device *dev; +}; + void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) { u32 axictl; @@ -235,9 +254,132 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev) dev_info(drvdata->dev, "TMC-ETR disabled\n"); } +static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, int cpu, + void **pages, int nr_pages, bool overwrite) +{ + int node; + struct cs_etr_buffers *buf; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + if (cpu == -1) + cpu = smp_processor_id(); + node = cpu_to_node(cpu); + + /* Allocate memory structure for interaction with Perf */ + buf = kzalloc_node(sizeof(struct cs_etr_buffers), GFP_KERNEL, node); + if (!buf) + return NULL; + + buf->dev = drvdata->dev; + buf->size = drvdata->size; + buf->vaddr = dma_alloc_coherent(buf->dev, buf->size, + &buf->paddr, GFP_KERNEL); + if (!buf->vaddr) { + kfree(buf); + return NULL; + } + + buf->tmc.snapshot = overwrite; + buf->tmc.nr_pages = nr_pages; + buf->tmc.data_pages = pages; + + return buf; +} + +static void tmc_free_etr_buffer(void *config) +{ + struct cs_etr_buffers *buf = config; + + dma_free_coherent(buf->dev, buf->size, buf->vaddr, buf->paddr); + kfree(buf); +} + +static int tmc_set_etr_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config) +{ + int ret = 0; + unsigned long head; + struct cs_etr_buffers *buf = sink_config; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + /* wrap head around to the amount of space we have */ + head = handle->head & ((buf->tmc.nr_pages << PAGE_SHIFT) - 1); + + /* find the page to write to */ + buf->tmc.cur = head / PAGE_SIZE; + + /* and offset within that page */ + buf->tmc.offset = head % PAGE_SIZE; + + local_set(&buf->tmc.data_size, 0); + + /* Tell the HW where to put the trace data */ + drvdata->vaddr = buf->vaddr; + drvdata->paddr = buf->paddr; + memset(drvdata->vaddr, 0, drvdata->size); + + return ret; +} + +static unsigned long tmc_reset_etr_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config, bool *lost) +{ + unsigned long size = 0; + struct cs_etr_buffers *buf = sink_config; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + if (buf) { + /* + * In snapshot mode ->data_size holds the new address of the + * ring buffer's head. The size itself is the whole address + * range since we want the latest information. + */ + if (buf->tmc.snapshot) { + size = buf->tmc.nr_pages << PAGE_SHIFT; + handle->head = local_xchg(&buf->tmc.data_size, size); + } + + /* + * Tell the tracer PMU how much we got in this run and if + * something went wrong along the way. Nobody else can use + * this cs_etr_buffers instance until we are done. As such + * resetting parameters here and squaring off with the ring + * buffer API in the tracer PMU is fine. + */ + *lost = !!local_xchg(&buf->tmc.lost, 0); + size = local_xchg(&buf->tmc.data_size, 0); + } + + /* Get ready for another run */ + drvdata->vaddr = NULL; + drvdata->paddr = 0; + + return size; +} + +static void tmc_update_etr_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config) +{ + struct cs_etr_buffers *buf = sink_config; + + /* + * An ETR configured to work in contiguous memory mode works the same + * was as an ETB or ETF. + */ + tmc_update_etf_buffer(csdev, handle, &buf->tmc); +} + static const struct coresight_ops_sink tmc_etr_sink_ops = { .enable = tmc_enable_etr_sink, .disable = tmc_disable_etr_sink, + .alloc_buffer = tmc_alloc_etr_buffer, + .free_buffer = tmc_free_etr_buffer, + .set_buffer = tmc_set_etr_buffer, + .reset_buffer = tmc_reset_etr_buffer, + .update_buffer = tmc_update_etr_buffer, }; const struct coresight_ops tmc_etr_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 62d568195e8e..8f4ab9b511f2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -153,6 +153,9 @@ void tmc_disable_hw(struct tmc_drvdata *drvdata); /* ETB/ETF functions */ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata); +void tmc_update_etf_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config); extern const struct coresight_ops tmc_etb_cs_ops; extern const struct coresight_ops tmc_etf_cs_ops;