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[68.189.91.139]) by smtp.gmail.com with ESMTPSA id ud5sm58165904pac.11.2016.04.14.06.16.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Apr 2016 06:16:35 -0700 (PDT) From: Tim Harvey To: Shawn Guo Subject: [PATCH] ARM: dts: imx: ventana: add RS485 txen gpio support Date: Thu, 14 Apr 2016 06:19:09 -0700 Message-Id: <1460639949-26392-1-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160414_061657_074779_36A7A055 X-CRM114-Status: GOOD ( 10.65 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, Sascha Hauer , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The GW52xx/GW53xx/GW54xx have an on-board RS485 transceiver for half-duplex RS485 using uart1. The active-high TXEN is GPIO7__IO1 which we can configure as the rts-gpio as long as we specify it as active-low to invert the polarity managed by mctrl_gpio helpers. This allows for RS485 to be used from userspace by setting flags to SER_RS485_RTS_ON_SEND in the serial_rs485 struct when using the TIOCGRS485 ioctl. Signed-off-by: Tim Harvey --- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 3 +++ arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 3 +++ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 3 +++ 3 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 8cccc4a..50d6039 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -315,6 +315,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + rts-gpio = <&gpio7 1 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -493,6 +495,7 @@ fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 5f700cc..60b0ae9 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -312,6 +312,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + rts-gpio = <&gpio7 1 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -482,6 +484,7 @@ fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index d19b4cc..c217ecc 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -414,6 +414,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + rts-gpio = <&gpio7 1 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -603,6 +605,7 @@ fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ >; };