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Fri, 15 Apr 2016 15:32:58 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, tomasz.figa@gmail.com, s.nawrocki@samsung.com, kgene@kernel.org Subject: [PATCH v2 6/8] clk: samsung: exynos542x: Add the clock id for ACLK Date: Fri, 15 Apr 2016 15:32:53 +0900 Message-id: <1460701975-24178-7-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1460701975-24178-1-git-send-email-cw00.choi@samsung.com> References: <1460701975-24178-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrAIsWRmVeSWpSXmKPExsWyRsSkUFe6WyDcoPmKgMX1L89ZLeYfOcdq 0f9mIavFuVcrGS0m3Z/AYvH6haFF/+PXzBZnm96wW2x6fI3V4vKuOWwWn3uPMFrMOL+PyWLd xlvsFrcv81q8PPKD0WLp9YtMFrcbV7BZTJi+lsXizOlLrBate4+wW/zfs4Pd4vCbdlaLttUf WC1W7frD6CDhsWbeGkaPluYeNo/Lfb1MHrfu1HvsnHWX3WPl8i9sHptWdbJ5bF5S7/HvGLvH lqvtLB59W1YxenzeJBfAE8Vlk5Kak1mWWqRvl8CVsbV3AnvBHp2Ko3snMTUwrlfrYuTkkBAw kehdt48NwhaTuHBvPZDNxSEksIJR4uHON2wwRVPP7mOHSMxilJjz5h4jhPOFUeJ+9zsWkCo2 AS2J/S9ugLWLCExllDjYPQusilngKrPEksY2dpAqYQFviVOzpjCB2CwCqhL7n85g7WLk4OAV cJX4udAPYp2cxIc9j8DKOQXcJBZNvs4IYgsBlbTMmwe2QELgDIdEy/IOqDkCEt8mH2IBmSMh ICux6QAzxBxJiYMrbrBMYBRewMiwilE0tSC5oDgpvchUrzgxt7g0L10vOT93EyMwok//ezZx B+P9A9aHGAU4GJV4eB/ECoQLsSaWFVfmHmI0BdowkVlKNDkfmDbySuINjc2MLExNTI2NzC3N lMR5daR/BgsJpCeWpGanphakFsUXleakFh9iZOLglAIGdHTJWeULajcdDBWXzeITW7g91ELC wF/OQU8u7nBJY/o316XHKn8keJ45/eUZ5yet9VUO/zkXib/7/0DAlWvW2/uxGQY1r/7qHr3P G+DcUT9z4bLFT+0nTi3VubhfPVCntTMiTePTx43FTjX9dyaZXuPaJLz41f/c1Q+vSXVn+l7a eShXSi5WiaU4I9FQi7moOBEABQQT/+MCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLKsWRmVeSWpSXmKPExsVy+t9jQV3pboFwg99dnBbXvzxntZh/5Byr Rf+bhawW516tZLSYdH8Ci8XrF4YW/Y9fM1ucbXrDbrHp8TVWi8u75rBZfO49wmgx4/w+Jot1 G2+xW9y+zGvx8sgPRoul1y8yWdxuXMFmMWH6WhaLM6cvsVq07j3CbvF/zw52i8Nv2lkt2lZ/ YLVYtesPo4OEx5p5axg9Wpp72Dwu9/Uyedy6U++xc9Zddo+Vy7+weWxa1cnmsXlJvce/Y+we W662s3j0bVnF6PF5k1wAT1QDo01GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5kkJe Ym6qrZKLT4CuW2YO0OtKCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6jAzQQMIaxoyt vRPYC/boVBzdO4mpgXG9WhcjJ4eEgInE1LP72CFsMYkL99azdTFycQgJzGKUmPPmHiOE84VR 4n73OxaQKjYBLYn9L26AVYkITGWUONg9C6yKWeAqs8SSxjawWcIC3hKnZk1hArFZBFQl9j+d wdrFyMHBK+Aq8XOhH8Q6OYkPex6BlXMKuEksmnydEcQWAippmTePbQIj7wJGhlWMEqkFyQXF Sem5Rnmp5XrFibnFpXnpesn5uZsYwUnjmfQOxsO73A8xCnAwKvHwPogVCBdiTSwrrsw9xCjB wawkwju5FSjEm5JYWZValB9fVJqTWnyI0RToronMUqLJ+cCEllcSb2hsYmZkaWRuaGFkbK4k zvv4/7owIYH0xJLU7NTUgtQimD4mDk6pBkaL9r+BH2UfzzlrdMskm+Odzt7ERdPs1qZJVEuI r9oT9c89emaShEzaLeEpAvNEozNksp/p/y3cfvv8o3OveQNTHj8skFvVUhC65GfyxOCEra4Z 030uS/eFXm1+dy7uSlr7o2Ll/7I3ttc+Wd1w7UxfrOWp1TF1KjESZYWnxb4+rKhYP6UlXEKJ pTgj0VCLuag4EQA4SWZ5MAMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160414_233322_671777_B7B8EB8A X-CRM114-Status: GOOD ( 11.48 ) X-Spam-Score: -7.9 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux-samsung-soc@vger.kernel.org, linux@arm.linux.org.uk, cw00.choi@samsung.com, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux.amoon@gmail.com, linux-pm@vger.kernel.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, devicetree@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, inki.dae@samsung.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the clock id for ACLK clock which is source clock of AMBA AXI Bus. This clock should be handled in Bus frequency scaling driver. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Tested-by: Markus Reichl Tested-by: Anand Moon Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5420.c | 77 ++++++++++++++++++++++-------------- 1 file changed, 47 insertions(+), 30 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index be03ed0fcb6b..92382cef9f90 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -554,8 +554,8 @@ static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { }; static struct samsung_div_clock exynos5800_div_clks[] __initdata = { - DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), - + DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", + "mout_aclk400_wcore", DIV_TOP0, 16, 3), DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", DIV_TOP8, 16, 3), DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", @@ -607,8 +607,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { }; static struct samsung_div_clock exynos5420_div_clks[] __initdata = { - DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll", - DIV_TOP0, 16, 3), + DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", + "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), }; static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { @@ -785,31 +785,47 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = { DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), - DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), - DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), - DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), - DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), - DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3), - DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), - DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), - - DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", - DIV_TOP1, 0, 3), - DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp", - DIV_TOP1, 4, 3), - DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), - DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0", - DIV_TOP1, 16, 3), - DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), - DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), - DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), - - DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), - DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), - DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), - DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), - DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3), - DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), + DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", + DIV_TOP0, 0, 3), + DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", + DIV_TOP0, 4, 3), + DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", + DIV_TOP0, 8, 3), + DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", + DIV_TOP0, 12, 3), + DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", + DIV_TOP0, 20, 3), + DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", + DIV_TOP0, 24, 3), + DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", + DIV_TOP0, 28, 3), + DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", + "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), + DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", + "mout_aclk333_432_isp", DIV_TOP1, 4, 3), + DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", + DIV_TOP1, 8, 6), + DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", + "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), + DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", + DIV_TOP1, 20, 3), + DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", + DIV_TOP1, 24, 3), + DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", + DIV_TOP1, 28, 3), + + DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", + DIV_TOP2, 8, 3), + DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", + DIV_TOP2, 12, 3), + DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, + 16, 3), + DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", + DIV_TOP2, 20, 3), + DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", + "mout_aclk300_disp1", DIV_TOP2, 24, 3), + DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", + DIV_TOP2, 28, 3), /* DISP1 Block */ DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), @@ -817,7 +833,8 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = { DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), - DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), + DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", + "mout_aclk400_disp1", DIV_TOP2, 4, 3), /* Audio Block */ DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),