From patchwork Fri Apr 15 17:11:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 8854021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6F55C9F3A0 for ; Fri, 15 Apr 2016 17:48:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2925820204 for ; Fri, 15 Apr 2016 17:48:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A082C2021A for ; Fri, 15 Apr 2016 17:48:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ar7pA-0003MZ-Lt; Fri, 15 Apr 2016 17:46:32 +0000 Received: from merlin.infradead.org ([2001:4978:20e::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ar7hN-0005of-Fc for linux-arm-kernel@bombadil.infradead.org; Fri, 15 Apr 2016 17:38:29 +0000 Received: from foss.arm.com ([217.140.101.70]) by merlin.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1ar7Qo-0001kO-TU for linux-arm-kernel@lists.infradead.org; Fri, 15 Apr 2016 17:21:23 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9F0FC5D4; Fri, 15 Apr 2016 10:10:51 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.203.153]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 144043F21A; Fri, 15 Apr 2016 10:12:04 -0700 (PDT) From: Andre Przywara To: Christoffer Dall , Marc Zyngier Subject: [PATCH 12/45] KVM: arm/arm64: vgic-new: Add MMIO handling framework Date: Fri, 15 Apr 2016 18:11:23 +0100 Message-Id: <1460740316-8755-13-git-send-email-andre.przywara@arm.com> X-Mailer: git-send-email 2.7.3 In-Reply-To: <1460740316-8755-1-git-send-email-andre.przywara@arm.com> References: <1460740316-8755-1-git-send-email-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160415_132123_147340_C3FFE91A X-CRM114-Status: GOOD ( 23.25 ) X-Spam-Score: -7.9 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Eric Auger MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We register a kvm_io_bus device for the distributor and dispatch the calls to the actual register handler at runtime. Ideally we would register each register group directly with the kvm_io_bus framework, but currently we run into the limit of 1000 devices pretty quickly (with GICv3), so we use this approach here, at least for the time being. Signed-off-by: Andre Przywara Signed-off-by: Eric Auger Changelog RFC..v1: - rework MMIO dispatching to use only one kvm_io_bus device - document purpose of register region macros - rename "this" parameter to "dev" - change IGROUPR to be RAO (returning 1 => Group1 IRQs) --- include/kvm/vgic/vgic.h | 9 ++ virt/kvm/arm/vgic/vgic_mmio.c | 226 ++++++++++++++++++++++++++++++++++++++++++ virt/kvm/arm/vgic/vgic_mmio.h | 53 ++++++++++ 3 files changed, 288 insertions(+) create mode 100644 virt/kvm/arm/vgic/vgic_mmio.c create mode 100644 virt/kvm/arm/vgic/vgic_mmio.h diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h index 664004f..f331469 100644 --- a/include/kvm/vgic/vgic.h +++ b/include/kvm/vgic/vgic.h @@ -106,6 +106,12 @@ struct vgic_irq { enum vgic_irq_config config; /* Level or edge */ }; +struct vgic_io_device { + gpa_t base_addr; + struct kvm_vcpu *redist_vcpu; + struct kvm_io_device dev; +}; + struct vgic_dist { bool in_kernel; bool ready; @@ -132,6 +138,9 @@ struct vgic_dist { u32 enabled; struct vgic_irq *spis; + + struct vgic_io_device dist_iodev; + struct vgic_io_device *redist_iodevs; }; struct vgic_v2_cpu_if { diff --git a/virt/kvm/arm/vgic/vgic_mmio.c b/virt/kvm/arm/vgic/vgic_mmio.c new file mode 100644 index 0000000..b70a274 --- /dev/null +++ b/virt/kvm/arm/vgic/vgic_mmio.c @@ -0,0 +1,226 @@ +/* + * VGIC MMIO handling functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include "vgic.h" +#include "vgic_mmio.h" + +void write_mask32(u32 value, int offset, int len, void *val) +{ + value = cpu_to_le32(value) >> (offset * 8); + memcpy(val, &value, len); +} + +u32 mask32(u32 origvalue, int offset, int len, const void *val) +{ + origvalue &= ~((BIT_ULL(len) - 1) << (offset * 8)); + memcpy((char *)&origvalue + (offset * 8), val, len); + return origvalue; +} + +#ifdef CONFIG_KVM_ARM_VGIC_V3 +void write_mask64(u64 value, int offset, int len, void *val) +{ + value = cpu_to_le64(value) >> (offset * 8); + memcpy(val, &value, len); +} + +/* FIXME: I am clearly misguided here, there must be some saner way ... */ +u64 mask64(u64 origvalue, int offset, int len, const void *val) +{ + origvalue &= ~((BIT_ULL(len) - 1) << (offset * 8)); + memcpy((char *)&origvalue + (offset * 8), val, len); + return origvalue; +} +#endif + +int vgic_mmio_read_raz(struct kvm_vcpu *vcpu, struct kvm_io_device *dev, + gpa_t addr, int len, void *val) +{ + memset(val, 0, len); + + return 0; +} + +int vgic_mmio_read_rao(struct kvm_vcpu *vcpu, struct kvm_io_device *dev, + gpa_t addr, int len, void *val) +{ + memset(val, 0xff, len); + + return 0; +} + +int vgic_mmio_write_wi(struct kvm_vcpu *vcpu, struct kvm_io_device *dev, + gpa_t addr, int len, const void *val) +{ + return 0; +} + +static int vgic_mmio_read_nyi(struct kvm_vcpu *vcpu, + struct kvm_io_device *dev, + gpa_t addr, int len, void *val) +{ + pr_warn("KVM: handling unimplemented VGIC MMIO read: VCPU %d, address: 0x%llx\n", + vcpu->vcpu_id, (unsigned long long)addr); + return 0; +} + +static int vgic_mmio_write_nyi(struct kvm_vcpu *vcpu, + struct kvm_io_device *dev, + gpa_t addr, int len, const void *val) +{ + pr_warn("KVM: handling unimplemented VGIC MMIO write: VCPU %d, address: 0x%llx\n", + vcpu->vcpu_id, (unsigned long long)addr); + return 0; +} + +struct vgic_register_region vgic_v2_dist_registers[] = { + REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 12), + REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP, + vgic_mmio_read_rao, vgic_mmio_write_wi, 1), + REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), + REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), + REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), + REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), + REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), + REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 1), + REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 8), + REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 8), + REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 8), + REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 4), + REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 16), + REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET, + vgic_mmio_read_nyi, vgic_mmio_write_nyi, 16), +}; + +/* Find the proper register handler entry given a certain address offset. */ +static struct vgic_register_region * +vgic_find_mmio_region(struct vgic_register_region *region, int nr_regions, + int offset) +{ + int i; + + for (i = 0; i < nr_regions; i++) { + int reg_size = region[i].len; + + if (!reg_size) + reg_size = (region[i].bits_per_irq * 1024) / 8; + + if ((offset < region[i].reg_offset) || + (offset >= region[i].reg_offset + reg_size)) + continue; + + return region + i; + } + + return NULL; +} + +static int dispatch_mmio_read(struct kvm_vcpu *vcpu, + struct vgic_register_region *regions, + int nr_regions, struct kvm_io_device *dev, + gpa_t addr, int len, void *val) +{ + struct vgic_io_device *iodev = container_of(dev, + struct vgic_io_device, dev); + struct vgic_register_region *region; + + region = vgic_find_mmio_region(regions, nr_regions, + addr - iodev->base_addr); + if (!region) + return -EOPNOTSUPP; + + return region->ops.read(vcpu, dev, addr, len, val); +} + +static int dispatch_mmio_write(struct kvm_vcpu *vcpu, + struct vgic_register_region *regions, + int nr_regions, struct kvm_io_device *dev, + gpa_t addr, int len, const void *val) +{ + struct vgic_io_device *iodev = container_of(dev, + struct vgic_io_device, dev); + struct vgic_register_region *region; + + region = vgic_find_mmio_region(regions, nr_regions, + addr - iodev->base_addr); + if (!region) + return -EOPNOTSUPP; + + return region->ops.write(vcpu, dev, addr, len, val); +} + +int vgic_mmio_read_v2dist(struct kvm_vcpu *vcpu, struct kvm_io_device *dev, + gpa_t addr, int len, void *val) +{ + return dispatch_mmio_read(vcpu, vgic_v2_dist_registers, + ARRAY_SIZE(vgic_v2_dist_registers), dev, + addr, len, val); +} + +int vgic_mmio_write_v2dist(struct kvm_vcpu *vcpu, struct kvm_io_device *dev, + gpa_t addr, int len, const void *val) +{ + return dispatch_mmio_write(vcpu, vgic_v2_dist_registers, + ARRAY_SIZE(vgic_v2_dist_registers), dev, + addr, len, val); +} + +struct kvm_io_device_ops kvm_io_v2dist_ops = { + .read = vgic_mmio_read_v2dist, + .write = vgic_mmio_write_v2dist, +}; + +int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address, + enum vgic_type type) +{ + struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev; + int ret = 0; + int len; + + switch (type) { + case VGIC_V2: + kvm_iodevice_init(&io_device->dev, &kvm_io_v2dist_ops); + len = SZ_4K; + break; + default: + BUG_ON(1); + } + + io_device->base_addr = dist_base_address; + + mutex_lock(&kvm->slots_lock); + ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address, + len, &io_device->dev); + mutex_unlock(&kvm->slots_lock); + + return ret; +} diff --git a/virt/kvm/arm/vgic/vgic_mmio.h b/virt/kvm/arm/vgic/vgic_mmio.h new file mode 100644 index 0000000..9b17e1b --- /dev/null +++ b/virt/kvm/arm/vgic/vgic_mmio.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __KVM_ARM_VGIC_MMIO_H__ +#define __KVM_ARM_VGIC_MMIO_H__ + +struct vgic_register_region { + int reg_offset; + int len; + int bits_per_irq; + struct kvm_io_device_ops ops; +}; + +/* + * Some VGIC registers store per-IRQ information, with a different number + * of bits per IRQ. For those registers this macro is used. + * The _WITH_LENGTH version instantiates registers with a fixed length + * and is mutually exclusive with the _PER_IRQ version. + */ +#define REGISTER_DESC_WITH_BITS_PER_IRQ(name, read_ops, write_ops, bpi) \ + {.reg_offset = name, .bits_per_irq = bpi, .len = 0, \ + .ops.read = read_ops, .ops.write = write_ops} +#define REGISTER_DESC_WITH_LENGTH(name, read_ops, write_ops, length) \ + {.reg_offset = name, .bits_per_irq = 0, .len = length, \ + .ops.read = read_ops, .ops.write = write_ops} + +int vgic_mmio_read_raz(struct kvm_vcpu *vcpu, struct kvm_io_device *this, + gpa_t addr, int len, void *val); +int vgic_mmio_write_wi(struct kvm_vcpu *vcpu, struct kvm_io_device *this, + gpa_t addr, int len, const void *val); +int kvm_vgic_register_mmio_region(struct kvm *kvm, struct kvm_vcpu *vcpu, + struct vgic_register_region *reg_desc, + struct vgic_io_device *region, + int nr_irqs, bool offset_private); + +void write_mask32(u32 value, int offset, int len, void *val); +void write_mask64(u64 value, int offset, int len, void *val); +u32 mask32(u32 origvalue, int offset, int len, const void *val); +u64 mask64(u64 origvalue, int offset, int len, const void *val); + +#endif