diff mbox

ARM: SoCFPGA: Fix secondary CPU startup in thumb2 kernel

Message ID 1461159271-3764-1-git-send-email-s.hauer@pengutronix.de (mailing list archive)
State New, archived
Headers show

Commit Message

Sascha Hauer April 20, 2016, 1:34 p.m. UTC
The secondary CPU starts up in ARM mode. When the kernel is compiled in
thumb2 mode we have to explicitly compile the secondary startup
trampoline in ARM mode, otherwise the CPU will go to Nirvana.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reported-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Suggested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: stable@vger.kernel.org
---
 arch/arm/mach-socfpga/headsmp.S | 1 +
 1 file changed, 1 insertion(+)

Comments

dinguyen@opensource.altera.com April 20, 2016, 4:18 p.m. UTC | #1
On 04/20/2016 08:34 AM, Sascha Hauer wrote:
> The secondary CPU starts up in ARM mode. When the kernel is compiled in
> thumb2 mode we have to explicitly compile the secondary startup
> trampoline in ARM mode, otherwise the CPU will go to Nirvana.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> Reported-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> Suggested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: stable@vger.kernel.org
> ---
>  arch/arm/mach-socfpga/headsmp.S | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
> index 5d94b7a..c160fa3 100644
> --- a/arch/arm/mach-socfpga/headsmp.S
> +++ b/arch/arm/mach-socfpga/headsmp.S
> @@ -13,6 +13,7 @@
>  #include <asm/assembler.h>
>  
>  	.arch	armv7-a
> +	.arm
>  
>  ENTRY(secondary_trampoline)
>  	/* CPU1 will always fetch from 0x0 when it is brought out of reset.
> 

Applied!

Thanks,
Dinh
diff mbox

Patch

diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index 5d94b7a..c160fa3 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -13,6 +13,7 @@ 
 #include <asm/assembler.h>
 
 	.arch	armv7-a
+	.arm
 
 ENTRY(secondary_trampoline)
 	/* CPU1 will always fetch from 0x0 when it is brought out of reset.