From patchwork Tue May 3 23:47:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 9008861 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 28C809F65D for ; Tue, 3 May 2016 23:49:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5C7C62037E for ; Tue, 3 May 2016 23:49:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8FE43200D9 for ; Tue, 3 May 2016 23:49:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1axk3D-0005Md-By; Tue, 03 May 2016 23:48:23 +0000 Received: from mail-gw2-out.broadcom.com ([216.31.210.63]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1axk3A-0005Gg-4M for linux-arm-kernel@lists.infradead.org; Tue, 03 May 2016 23:48:20 +0000 X-IronPort-AV: E=Sophos;i="5.24,574,1455004800"; d="scan'208";a="94648255" Received: from mail-irv-18.broadcom.com ([10.15.198.37]) by mail-gw2-out.broadcom.com with ESMTP; 03 May 2016 17:01:44 -0700 Received: from mail-irva-12.broadcom.com (mail-irva-12.broadcom.com [10.11.16.101]) by mail-irv-18.broadcom.com (Postfix) with ESMTP id 39CAC82028; Tue, 3 May 2016 16:47:59 -0700 (PDT) Received: from smtphost.broadcom.com (lbrmn-lnxub44.ric.broadcom.com [10.136.8.49]) by mail-irva-12.broadcom.com (Postfix) with ESMTP id 7895E12764C; Tue, 3 May 2016 16:47:28 -0700 (PDT) From: Ray Jui To: Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH 1/2] dt-bindings: arm, gic: Indtroduce optional property 'arm, msi-offset-spi' for gicv2m Date: Tue, 3 May 2016 16:47:24 -0700 Message-Id: <1462319245-32532-2-git-send-email-ray.jui@broadcom.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1462319245-32532-1-git-send-email-ray.jui@broadcom.com> References: <1462319245-32532-1-git-send-email-ray.jui@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160503_164820_215883_FC98F902 X-CRM114-Status: UNSURE ( 8.03 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -5.2 (-----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ray Jui , bcm-kernel-feedback-list@broadcom.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alex Barba MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update the GICv2m binding document by adding an optional property 'arm,msi-offset-spi'. Some implementations of gicv2m have an erratum where the MSI data is the SPI number subtracted by an offset. This is required for the correct MSI interrupt to be triggered. Signed-off-by: Ray Jui --- Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt index 793c20f..550960f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt @@ -140,6 +140,12 @@ Optional properties: value, this property should contain the number of SPIs assigned to the frame, overriding the HW value. +- arm,msi-offset-spi: Some implementations of gicv2m have an erratum where + the MSI data is the SPI number subtracted by an offset. + This is required for the correct MSI interrupt to be + triggered. This property should contain the required + offset. + Example: interrupt-controller@e1101000 {