From patchwork Thu May 5 20:12:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 9027221 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id ACD949F1D3 for ; Thu, 5 May 2016 20:14:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C7DE6203B4 for ; Thu, 5 May 2016 20:14:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 08221203A5 for ; Thu, 5 May 2016 20:14:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ayPdl-0007FH-ON; Thu, 05 May 2016 20:12:53 +0000 Received: from mail.kmu-office.ch ([178.209.48.109]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ayPdj-00072H-E7 for linux-arm-kernel@lists.infradead.org; Thu, 05 May 2016 20:12:52 +0000 Received: from trochilidae.toradex.int (75-146-58-181-Washington.hfc.comcastbusiness.net [75.146.58.181]) by mail.kmu-office.ch (Postfix) with ESMTPSA id 94ACC5C0221; Thu, 5 May 2016 22:10:27 +0200 (CEST) From: Stefan Agner To: shawnguo@kernel.org Subject: [PATCH] ARM: dts: imx7d-pinfunc: add input mux for UART2 RX DTE mode Date: Thu, 5 May 2016 13:12:24 -0700 Message-Id: <1462479144-2481-1-git-send-email-stefan@agner.ch> X-Mailer: git-send-email 2.8.2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=agner.ch; s=dkim; t=1462479029; bh=6jYD+jeiU1bawbq4t17FjAseosmS4aWOaPLfunjbeFQ=; h=From:To:Cc:Subject:Date:Message-Id; b=DM6SsUN0dxSOleO5nWRAfnnzDQaFWDsJAqh7hkE6Mu5KKJEEBTEr7O7Q80ElmnbTdKXv0nOnjlS6ckhb5Qht7CHusU1iCcnPGKqYD7rW0NrCYIWFcWUKW8nWmznTXF49vdqHlxKrs34mtS8Oi67Hlum5w2j8nl5rssjkQHCMTbI= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160505_131251_651714_827BAC08 X-CRM114-Status: UNSURE ( 9.29 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.0 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, aalonso@freescale.com, Frank.Li@freescale.com, linux-kernel@vger.kernel.org, Stefan Agner , kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add input mux for UART2 RX in DTE mode. This allows to use the pad UART2_TX_DATA_ALT0 as UART2 RX. This particular input select seems to be missing in current reference manuals (Rev. B), but when looking at the tables and other UART input select registers (e.g. UART3) it seems naturally that this input mux register also has a fourth pad option for UART2_TX_DATA_ALT0. It has also been proven to be required to use UART2 in DTE mode and the particular pads on the Colibri iMX7 platform. Signed-off-by: Stefan Agner Acked-by: Frank Li --- arch/arm/boot/dts/imx7d-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index eeda783..3f9f0d9 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -594,7 +594,7 @@ #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 #define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0 #define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 #define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 #define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 #define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0