From patchwork Wed May 11 17:40:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylvain Lemieux X-Patchwork-Id: 9073731 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2049DBF29F for ; Wed, 11 May 2016 17:42:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 32AAC2010B for ; Wed, 11 May 2016 17:42:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 540BD20103 for ; Wed, 11 May 2016 17:42:11 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b0Y7o-0003F5-0l; Wed, 11 May 2016 17:40:44 +0000 Received: from mail-io0-x242.google.com ([2607:f8b0:4001:c06::242]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1b0Y7k-00038w-FX for linux-arm-kernel@lists.infradead.org; Wed, 11 May 2016 17:40:41 +0000 Received: by mail-io0-x242.google.com with SMTP id i75so6537677ioa.2 for ; Wed, 11 May 2016 10:40:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=5zgT3VWvFQgxHPAjbvH7QeO4XOdnO3awQRtG/Wd24kk=; b=nUzLWTsSM61UoNdI8mUYy0VDIOavy2oJN1WfDGDUvWT6GZrpNvWSMi3MwINGx3LkE/ i3G64Jp785n2hz2Sb/E3IUkpmrqU4Gjpt4vUvVWQFEOstOBOknVZFVQr8dg5i+vKf8yJ KKXCaL/1pC0iVaFAERhDLRgmJKWU29KjfiEbRRYaiIhCBMa9JMfd4iTzb6yLl9G/UQNm l621G6Z5t45E0JxV05LAABfHdcBmuTKoSHJ9HIcvYsP1S0qwN4Kgqr0a3qcGbVFnQ2vp yQ+yfN9TCwLqqSP1iM6zaB2Gr3GoZviszT0amLT3Uy6JPEGLOyIni5FvSXh/vVCiLUhr sa9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=5zgT3VWvFQgxHPAjbvH7QeO4XOdnO3awQRtG/Wd24kk=; b=EgJRNZTKovgdxZiDE2SwX5vKuscojaWErH8JAD+ohV4XO9V96GhbIVmLE77q24rrKe 8PUCrXHIeKPalwRF3MAARKaWeJvy1os/Av2Rtr+MJ8AVyGxYjsgcA7YOKRFVZ4/42JN6 99zYxbIA8aUTnzl1hfoPNR235kerAqpAsEcGFHVq2riPBJ4ML1Hp5oS50mEhROfpaUa9 9rb3IxbHrBEOekpAdOfZR4QhknSumBhcAuYag11k88ZisEXx80NgdMuZCDwx9XkrQxOr T70mj+LwdrMEx1RsDm/mTG+MZQ7XVWgxpTUHkLljNQzaz/2Iy50cY2tSGOI3UfRhUcO7 GIEA== X-Gm-Message-State: AOPr4FVCTQ7HYKVyjLvuJA0OPZiefzXdegi7qtyDxGiI53gWe3O8G/pRKKDKUkLbk8qj0g== X-Received: by 10.36.112.199 with SMTP id f190mr5644840itc.6.1462988418756; Wed, 11 May 2016 10:40:18 -0700 (PDT) Received: from CABRO3AP00510.americas.tsp.ad ([74.51.240.241]) by smtp.gmail.com with ESMTPSA id 142sm1703834itk.12.2016.05.11.10.40.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 May 2016 10:40:17 -0700 (PDT) From: Sylvain Lemieux To: vz@mleia.com, linus.walleij@linaro.org, gnurou@gmail.com Subject: [PATCH] gpio: lpc32xx: disable broken to_irq support Date: Wed, 11 May 2016 13:40:00 -0400 Message-Id: <1462988400-21738-1-git-send-email-slemieux.tyco@gmail.com> X-Mailer: git-send-email 1.8.3.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160511_104040_600151_0D370BC7 X-CRM114-Status: GOOD ( 12.60 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_WEB, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sylvain Lemieux The "to_irq" functionality is broken inside this driver since commit 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"). The addition of the new lpc32xx irqchip driver in 4.7, fixed the lpc32xx platform interrupt issue. When switching to the new lpc32xx irqchip driver, a warning appear in the lpc32xx gpio driver: warning: "NR_IRQS" redefined. To remove this warning (temporary solution), this patch disables the broken "to_irq" mapping functionality support. Signed-off-by: Sylvain Lemieux --- Note: * For details on the lpc32xx irqchip patch, refer to: http://thread.gmane.org/gmane.linux.drivers.devicetree/165620 * The final solution is to replace the existing lpc32xx gpio driver. This work is currently in progress; refer to the following URL: http://thread.gmane.org/gmane.linux.drivers.devicetree/144696 drivers/gpio/gpio-lpc32xx.c | 48 +-------------------------------------------- 1 file changed, 1 insertion(+), 47 deletions(-) diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c index d39014d..fc5f197 100644 --- a/drivers/gpio/gpio-lpc32xx.c +++ b/drivers/gpio/gpio-lpc32xx.c @@ -29,7 +29,6 @@ #include #include -#include #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) @@ -371,61 +370,16 @@ static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset) { - return IRQ_LPC32XX_P0_P1_IRQ; + return -ENXIO; } -static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = { - IRQ_LPC32XX_GPIO_00, - IRQ_LPC32XX_GPIO_01, - IRQ_LPC32XX_GPIO_02, - IRQ_LPC32XX_GPIO_03, - IRQ_LPC32XX_GPIO_04, - IRQ_LPC32XX_GPIO_05, -}; - static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset) { - if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table)) - return lpc32xx_gpio_to_irq_gpio_p3_table[offset]; return -ENXIO; } -static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = { - IRQ_LPC32XX_GPI_00, - IRQ_LPC32XX_GPI_01, - IRQ_LPC32XX_GPI_02, - IRQ_LPC32XX_GPI_03, - IRQ_LPC32XX_GPI_04, - IRQ_LPC32XX_GPI_05, - IRQ_LPC32XX_GPI_06, - IRQ_LPC32XX_GPI_07, - IRQ_LPC32XX_GPI_08, - IRQ_LPC32XX_GPI_09, - -ENXIO, /* 10 */ - -ENXIO, /* 11 */ - -ENXIO, /* 12 */ - -ENXIO, /* 13 */ - -ENXIO, /* 14 */ - -ENXIO, /* 15 */ - -ENXIO, /* 16 */ - -ENXIO, /* 17 */ - -ENXIO, /* 18 */ - IRQ_LPC32XX_GPI_19, - -ENXIO, /* 20 */ - -ENXIO, /* 21 */ - -ENXIO, /* 22 */ - -ENXIO, /* 23 */ - -ENXIO, /* 24 */ - -ENXIO, /* 25 */ - -ENXIO, /* 26 */ - -ENXIO, /* 27 */ - IRQ_LPC32XX_GPI_28, -}; - static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset) { - if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table)) - return lpc32xx_gpio_to_irq_gpi_p3_table[offset]; return -ENXIO; }