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Thu, 12 May 2016 16:06:28 +0000 From: Yury Norov To: , Subject: [PATCH v2] arm64: fix current_thread_info()->addr_limit setup Date: Thu, 12 May 2016 19:06:03 +0300 Message-ID: <1463069163-374-1-git-send-email-ynorov@caviumnetworks.com> X-Mailer: git-send-email 2.5.0 MIME-Version: 1.0 X-Originating-IP: [95.143.213.121] X-ClientProxiedBy: HE1PR06CA0083.eurprd06.prod.outlook.com (10.164.28.179) To SN1PR07MB2239.namprd07.prod.outlook.com (10.164.47.145) X-MS-Office365-Filtering-Correlation-Id: 37ad1ed5-9448-4b31-0a8e-08d37a7f60dd X-Microsoft-Exchange-Diagnostics: 1; SN1PR07MB2239; 2:1/6rQTrOq8FeUJFoAhoWgHDqird6o1yEBGw4pijx1wWVsXJdoeShIacRn+pSz1s+z80vzOdkbWOmrvOsQdziSjIAHqu+r+rrQkfTIGyTbG14CpuL7A8JHpWpZhy5G3QyBXyXhev2c3ef7g0Y0q0rxucmnsXFx7CWUWjIGFjHtbLVWoSxTncj2JJTkrCgnBHn; 3:e2hgimYRvOQLZ3HB4y6cdFCBBrVp7FtKimOz/dkGSYBug6dyxvD2/bhgHv9reEAithAXaQ6PEnoAMq5cr1CPMwnQnpf56Ml6iWntMzQYzR6OZuuQyal/kPLifen2CkoJ; 25:qx44nAlhnkpLnf2NF2tnlap9Z0hKHONY0JWaVTbd4J6s8ykHK6IBBkFdPhVp9gCZGQEegHeF6W3Fwl1dA0UJ0fFW/8r/cgyZrTpMWBxNrL3xm54TKLeNoiOSeQsTVT9YHBpRfH73Z3FBJIOGLinTYBzkQHYxEpxKkptk6N0sIIcSNPz750tIxVuRfc9dp6Xv6hdiRY79ITTS1e4mUppz8n/Tq2/AW/HVF7wXG5i27EH+bInkBFuUUY4b25/a4tu3s8TUvcutLTho1ejJnn2yoa3BlxA+gBrkyFKaAa1yrhTcGiZ4ynnpFAknjy/dFqb/oStY/ERRgmrZsAh3wvYiDd+NsipD6JTHKl1vL8ECSV1s98/uwJHzYavfd4VBMGq+a1lwmtG9XZuIt+T+h290qvaOlM9OXAYVI6JQTuBdAYY= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SN1PR07MB2239; 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SN1PR07MB2239; 5:UwpMsWtxSeqj7Aj7NfFoIXk1d1cAJ3E1e447G1v6h3ZFOBXs0rASTuE2WdnlHRiONE1vSHnC7kgJa/T8uaYpxBlsTrikKxxgP7ewmPE/JfEc3nEWs63mYVbAACoKP8JgZuE7Pj1SOAKInmKJqcaKLQ==; 24:85OHT4RctaGCorSIwHXEm1HR32B2/+7vZ/wpNevRMGFh42hbu+/62C9aakez7KdVHzPAWQQBs1j/FQXiwWB7vQqehGEA7Jr5K88P/gtJWV0=; 7:lcdAVYT0jgglWI/ko80SvI6td8ecsFjWuRZ8h+3pyzoz3NQ9/iDJiN2O2Fc6pJ6m3/FhpTIx3/Am+AQGRW677ouWHNf+o6pdCHG3YNPst5v7lxSmQ62TTlBXwJKFu6dgKbVQ3gZYgWmp1Qdgpn4YTxbFhGtrNFuTS+dlfudQsZDPLIMtNVXG4VxKKgHQIZOL SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2016 16:06:28.9218 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR07MB2239 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160512_090652_090519_B4E5A0D1 X-CRM114-Status: GOOD ( 10.37 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Yury Norov , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP At elf loading in flush_old_exec() in fs/exec.c, generic code sets current_thread_info()->addr_limit to one that corresponds aarch64 value, and ignores compat mode there as corresponding status setup happens later on in load_elf_binary() by SET_PERSONALITY() macro. As result, compat task has wrong addr_limit, and it may cause various bugs. This patch fixes it. It also fixes USER_DS macro to return different values depending on compat at runtime. It was discovered during ilp32 development. See details here: https://lkml.org/lkml/2016/5/11/975 v2: flush tpidrro_el0 unconditionally in tls_thread_flush() as if exec() is called by aarch64 task, is_compat_task() fails even if new thread is aarch32. Signed-off-by: Yury Norov --- arch/arm64/include/asm/elf.h | 11 +++++++++-- arch/arm64/include/asm/uaccess.h | 2 +- arch/arm64/kernel/process.c | 18 +++++++----------- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h index 24ed037..fda75ce 100644 --- a/arch/arm64/include/asm/elf.h +++ b/arch/arm64/include/asm/elf.h @@ -138,7 +138,10 @@ typedef struct user_fpsimd_state elf_fpregset_t; */ #define ELF_PLAT_INIT(_r, load_addr) (_r)->regs[0] = 0 -#define SET_PERSONALITY(ex) clear_thread_flag(TIF_32BIT); +#define SET_PERSONALITY(ex) do { \ + clear_thread_flag(TIF_32BIT); \ + set_fs(TASK_SIZE_64); \ +} while (0) #define ARCH_DLINFO \ do { \ @@ -181,7 +184,11 @@ typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG]; ((x)->e_flags & EF_ARM_EABI_MASK)) #define compat_start_thread compat_start_thread -#define COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT); +#define COMPAT_SET_PERSONALITY(ex) do { \ + set_thread_flag(TIF_32BIT); \ + set_fs(TASK_SIZE_32); \ +} while (0) + #define COMPAT_ARCH_DLINFO extern int aarch32_setup_vectors_page(struct linux_binprm *bprm, int uses_interp); diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 0685d74..5b269e6 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -60,7 +60,7 @@ extern int fixup_exception(struct pt_regs *regs); #define KERNEL_DS (-1UL) #define get_ds() (KERNEL_DS) -#define USER_DS TASK_SIZE_64 +#define USER_DS TASK_SIZE #define get_fs() (current_thread_info()->addr_limit) static inline void set_fs(mm_segment_t fs) diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 8062482..2b25930 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -211,17 +211,13 @@ static void tls_thread_flush(void) { asm ("msr tpidr_el0, xzr"); - if (is_compat_task()) { - current->thread.tp_value = 0; - - /* - * We need to ensure ordering between the shadow state and the - * hardware state, so that we don't corrupt the hardware state - * with a stale shadow state during context switch. - */ - barrier(); - asm ("msr tpidrro_el0, xzr"); - } + /* + * We need to ensure ordering between the shadow state and the + * hardware state, so that we don't corrupt the hardware state + * with a stale shadow state during context switch. + */ + barrier(); + asm ("msr tpidrro_el0, xzr"); } void flush_thread(void)