From patchwork Tue May 24 13:30:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: fu.wei@linaro.org X-Patchwork-Id: 9133651 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DA406607D5 for ; Tue, 24 May 2016 13:33:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CC1062821B for ; Tue, 24 May 2016 13:33:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C078A28288; Tue, 24 May 2016 13:33:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4D8772821B for ; Tue, 24 May 2016 13:33:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b5CRc-0007te-9Z; Tue, 24 May 2016 13:32:24 +0000 Received: from mx1.redhat.com ([209.132.183.28]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1b5CRB-0007L8-4P for linux-arm-kernel@lists.infradead.org; Tue, 24 May 2016 13:31:58 +0000 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A5A976408C; Tue, 24 May 2016 13:31:39 +0000 (UTC) Received: from magi-f23.redhat.com (vpn1-7-183.pek2.redhat.com [10.72.7.183]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u4ODUf9w015249; Tue, 24 May 2016 09:31:32 -0400 From: fu.wei@linaro.org To: rjw@rjwysocki.net, lenb@kernel.org, daniel.lezcano@linaro.org, tglx@linutronix.de, marc.zyngier@arm.com, hanjun.guo@linaro.org Subject: [PATCH v5 6/6] clocksource/drivers/arm_arch_timer: Add GTDT support for memory-mapped timer Date: Tue, 24 May 2016 21:30:33 +0800 Message-Id: <1464096633-9309-7-git-send-email-fu.wei@linaro.org> In-Reply-To: <1464096633-9309-1-git-send-email-fu.wei@linaro.org> References: <1464096633-9309-1-git-send-email-fu.wei@linaro.org> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 24 May 2016 13:31:39 +0000 (UTC) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160524_063157_342500_A55574CC X-CRM114-Status: GOOD ( 20.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, harba@codeaurora.org, Fu Wei , al.stone@linaro.org, graeme.gregory@linaro.org, linaro-acpi@lists.linaro.org, jcm@redhat.com, timur@codeaurora.org, will.deacon@arm.com, rruigrok@codeaurora.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, wim@iguana.be, arnd@arndb.de, cov@codeaurora.org, Suravee.Suthikulpanit@amd.com, catalin.marinas@arm.com, leo.duran@amd.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Fu Wei The patch add memory-mapped timer register support by using the information provided by the new GTDT driver of ACPI. Signed-off-by: Fu Wei --- drivers/clocksource/arm_arch_timer.c | 147 +++++++++++++++++++++++++++++++++-- 1 file changed, 142 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 505e65c..3ac0fda 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -849,24 +849,161 @@ CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", arch_timer_mem_init); #ifdef CONFIG_ACPI_GTDT -/* Initialize per-processor generic timer */ +static struct gt_timer_data __init *arch_timer_mem_get_timer( + struct gt_block_data *gt_blocks) +{ + struct gt_block_data *gt_block = gt_blocks; + struct gt_timer_data *best_frame = NULL; + void __iomem *cntctlbase; + u32 cnttidr; + int i; + + /* + * According to ARMv8 Architecture Reference Manual(ARM), + * the size of CNTCTLBase frame of memory-mapped timer + * is SZ_4K(Offset 0x000 – 0xFFF). + */ + cntctlbase = ioremap(gt_block->cntctlbase_phy, SZ_4K); + if (!cntctlbase) { + pr_err("Can't map CNTCTLBase\n"); + return NULL; + } + cnttidr = readl_relaxed(cntctlbase + CNTTIDR); + + /* + * Try to find a virtual capable frame. Otherwise fall back to a + * physical capable frame. + */ + for (i = 0; i < gt_block->timer_count; i++) { + int n; + u32 cntacr; + + n = gt_block->timer[i].frame_nr; + + /* Try enabling everything, and see what sticks */ + cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | + CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; + writel_relaxed(cntacr, cntctlbase + CNTACR(n)); + cntacr = readl_relaxed(cntctlbase + CNTACR(n)); + + if ((cnttidr & CNTTIDR_VIRT(n)) && + !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) { + best_frame = >_block->timer[i]; + arch_timer_mem_use_virtual = true; + break; + } + + if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) + continue; + + best_frame = >_block->timer[i]; + } + iounmap(cntctlbase); + + return best_frame; +} + +static int __init arch_timer_mem_acpi_init(u32 timer_count) +{ + struct gt_block_data *gt_blocks; + struct gt_timer_data *gt_timer; + void __iomem *timer_cntbase; + int ret = -EINVAL; + int timer_irq; + + /* + * If we have some Platform Timer Structures, + * try to find and register a memory-mapped timer. + * If not, just return. + */ + if (!timer_count) + return 0; + + if (arch_timers_present & ARCH_MEM_TIMER) { + pr_warn("memory-mapped timer already initialized, skipping\n"); + return 0; + } + arch_timers_present |= ARCH_MEM_TIMER; + /* + * before really check all the Platform Timer Structures, + * we assume they are GT block, and allocate memory for them. + * We will free these memory once we finish the initialization. + */ + gt_blocks = kcalloc(timer_count, sizeof(*gt_blocks), GFP_KERNEL); + if (!gt_blocks) + return -ENOMEM; + + if (gtdt_arch_timer_mem_init(gt_blocks)) { + gt_timer = arch_timer_mem_get_timer(gt_blocks); + if (!gt_timer) { + pr_err("Failed to get mem timer info.\n"); + goto error; + } + + if (arch_timer_mem_use_virtual) + timer_irq = gt_timer->virt_irq; + else + timer_irq = gt_timer->irq; + if (!timer_irq) { + pr_err("Frame missing %s irq", + arch_timer_mem_use_virtual ? "virt" : "phys"); + goto error; + } + + /* + * According to ARMv8 Architecture Reference Manual(ARM), + * the size of CNTBaseN frames of memory-mapped timer + * is SZ_4K(Offset 0x000 – 0xFFF). + */ + timer_cntbase = ioremap(gt_timer->cntbase_phy, SZ_4K); + if (!timer_cntbase) { + pr_err("Can't map CntBase.\n"); + goto error; + } + arch_counter_base = timer_cntbase; + ret = arch_timer_mem_register(timer_cntbase, timer_irq); + if (ret) { + iounmap(timer_cntbase); + arch_counter_base = NULL; + pr_err("Failed to register mem timer.\n"); + } + } + +error: + kfree(gt_blocks); + return ret; +} + +/* Initialize per-processor generic timer and memory-mapped timer(if present) */ static int __init arch_timer_acpi_init(struct acpi_table_header *table) { + u32 timer_count; + if (arch_timers_present & ARCH_CP15_TIMER) { pr_warn("already initialized, skipping\n"); return -EINVAL; } - arch_timers_present |= ARCH_CP15_TIMER; + /* + * Get the per-processor generic timer info. + */ if (gtdt_arch_timer_init(table, arch_timer_ppi, &arch_timer_c3stop, - NULL)) + &timer_count)) return -EINVAL; - /* Get the frequency from CNTFRQ */ + /* + * Because in a system that implements both Secure and + * Non-secure states, CNTFRQ is only accessible in Secure state. + * So we just try to get the system counter frequency from cntfrq_el0 + * (system coprocessor register) here . + */ arch_timer_detect_rate(NULL, NULL); - arch_timer_init(); + if (arch_timer_mem_acpi_init(timer_count)) + pr_err("Failed to initialize memory-mapped timer, skipping\n"); + + arch_timer_init(); return 0; } CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);