From patchwork Wed May 25 09:50:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 9135077 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6E89F60221 for ; Wed, 25 May 2016 09:54:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6191428110 for ; Wed, 25 May 2016 09:54:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5487B282D7; Wed, 25 May 2016 09:54:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DEB2C28110 for ; Wed, 25 May 2016 09:54:35 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b5VUn-00023x-Kk; Wed, 25 May 2016 09:52:57 +0000 Received: from mail-pa0-f65.google.com ([209.85.220.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1b5VSl-0007uL-EN; Wed, 25 May 2016 09:50:56 +0000 Received: by mail-pa0-f65.google.com with SMTP id gp3so4659661pac.2; Wed, 25 May 2016 02:50:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q2Pra7PeBk/GBe14lnyiIm+7rkPXq951vtvy6Dq8frA=; b=FRqEjQhsoEcI81SM4EW8FRjcCiFGwN18ZG3EuLfW+pQF1zjmTHwXiRVbzF1+oIhqcG Abdopq/VZbrR8klBwRFt3v/w2TDDobM+E1T93SUdkfkgBeZKPQtzoBf+eFoaSRKNzVV4 oz0r/b1byLwvSwVhKh8sQxMHhzuxM0NGe5u99PH/dSAJ/E44eCrDzH8cTq83hgbZcqoh Va40qy0gsPM+Mwl3sgeVoHWndtnGMCX2bTM8OxpPuwF9jAsB0Uqv9uW5nRwe3t7Qjctk fIMQmuAwCrAYzlOwP99DXGH40LD6aRAXdn1z5ADkTX8p1fzzlrZ7YjHiT90ZuDT576f5 DYGA== X-Gm-Message-State: ALyK8tLhNFUpCDS6987HJ73PpbLSfzIFFomQFMxE+tlo2s0t/pUkH2vL47ftyXp9xtH8Qg== X-Received: by 10.66.240.8 with SMTP id vw8mr4407973pac.62.1464169832039; Wed, 25 May 2016 02:50:32 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id t8sm11406898paw.16.2016.05.25.02.50.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 May 2016 02:50:31 -0700 (PDT) From: Caesar Wang To: daniel.lezcano@linaro.org, Heiko Stuebner Subject: [PATCH 4/5] clocksource: rockchip: add support for rk3399 SoC Date: Wed, 25 May 2016 17:50:01 +0800 Message-Id: <1464169802-6033-5-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464169802-6033-1-git-send-email-wxt@rock-chips.com> References: <1464169802-6033-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160525_025052_088367_A1D977BD X-CRM114-Status: GOOD ( 14.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangtao@rock-chips.com, dianders@chromium.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, smbarber@google.com, cf@rock-chips.com, briannorris@google.com, Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Caesar Wang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Huang Tao The CONTROL register offset is different from old SoCs. For Linux driver, there are not functional changes at all. Let's call it v2. Signed-off-by: Huang Tao Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Heiko Stuebner Tested-by: Jianqun Xu Signed-off-by: Caesar Wang --- drivers/clocksource/rockchip_timer.c | 112 ++++++++++++++++++++++++++++------- 1 file changed, 91 insertions(+), 21 deletions(-) diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c index f3dfb1a..7ce1d08 100644 --- a/drivers/clocksource/rockchip_timer.c +++ b/drivers/clocksource/rockchip_timer.c @@ -19,8 +19,9 @@ #define TIMER_LOAD_COUNT0 0x00 #define TIMER_LOAD_COUNT1 0x04 -#define TIMER_CONTROL_REG 0x10 +#define TIMER_V1_CONTROL_REG 0x10 #define TIMER_INT_STATUS 0x18 +#define TIMER_V2_CONTROL_REG 0x1c #define TIMER_DISABLE 0x0 #define TIMER_ENABLE 0x1 @@ -46,15 +47,26 @@ static inline void __iomem *rk_base(struct clock_event_device *ce) return rk_timer(ce)->base; } -static inline void rk_timer_disable(struct clock_event_device *ce) +static inline void rk_timer_v1_disable(struct clock_event_device *ce) { - writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG); + writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_V1_CONTROL_REG); } -static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags) +static inline void rk_timer_v1_enable(struct clock_event_device *ce, u32 flags) { writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags, - rk_base(ce) + TIMER_CONTROL_REG); + rk_base(ce) + TIMER_V1_CONTROL_REG); +} + +static inline void rk_timer_v2_disable(struct clock_event_device *ce) +{ + writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_V2_CONTROL_REG); +} + +static inline void rk_timer_v2_enable(struct clock_event_device *ce, u32 flags) +{ + writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags, + rk_base(ce) + TIMER_V2_CONTROL_REG); } static void rk_timer_update_counter(unsigned long cycles, @@ -69,44 +81,82 @@ static void rk_timer_interrupt_clear(struct clock_event_device *ce) writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS); } -static inline int rk_timer_set_next_event(unsigned long cycles, - struct clock_event_device *ce) +static int rk_timer_v1_set_next_event(unsigned long cycles, + struct clock_event_device *ce) { - rk_timer_disable(ce); + rk_timer_v1_disable(ce); rk_timer_update_counter(cycles, ce); - rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT); + rk_timer_v1_enable(ce, TIMER_MODE_USER_DEFINED_COUNT); return 0; } -static int rk_timer_shutdown(struct clock_event_device *ce) +static int rk_timer_v1_shutdown(struct clock_event_device *ce) { - rk_timer_disable(ce); + rk_timer_v1_disable(ce); return 0; } -static int rk_timer_set_periodic(struct clock_event_device *ce) +static int rk_timer_v1_set_periodic(struct clock_event_device *ce) { - rk_timer_disable(ce); + rk_timer_v1_disable(ce); rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce); - rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING); + rk_timer_v1_enable(ce, TIMER_MODE_FREE_RUNNING); return 0; } -static irqreturn_t rk_timer_interrupt(int irq, void *dev_id) +static irqreturn_t rk_timer_v1_interrupt(int irq, void *dev_id) { struct clock_event_device *ce = dev_id; rk_timer_interrupt_clear(ce); if (clockevent_state_oneshot(ce)) - rk_timer_disable(ce); + rk_timer_v1_disable(ce); ce->event_handler(ce); return IRQ_HANDLED; } -static void __init rk_timer_init(struct device_node *np) +static int rk_timer_v2_set_next_event(unsigned long cycles, + struct clock_event_device *ce) +{ + rk_timer_v2_disable(ce); + rk_timer_update_counter(cycles, ce); + rk_timer_v2_enable(ce, TIMER_MODE_USER_DEFINED_COUNT); + return 0; +} + +static int rk_timer_v2_shutdown(struct clock_event_device *ce) +{ + rk_timer_v2_disable(ce); + return 0; +} + +static int rk_timer_v2_set_periodic(struct clock_event_device *ce) +{ + rk_timer_v2_disable(ce); + rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce); + rk_timer_v2_enable(ce, TIMER_MODE_FREE_RUNNING); + return 0; +} + +static irqreturn_t rk_timer_v2_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *ce = dev_id; + + rk_timer_interrupt_clear(ce); + + if (clockevent_state_oneshot(ce)) + rk_timer_v2_disable(ce); + + ce->event_handler(ce); + + return IRQ_HANDLED; +} + +static void __init rk_timer_init(struct device_node *np, + irq_handler_t rk_timer_interrupt) { struct clock_event_device *ce = &bc_timer.ce; struct clk *timer_clk; @@ -152,9 +202,6 @@ static void __init rk_timer_init(struct device_node *np) ce->name = TIMER_NAME; ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ; - ce->set_next_event = rk_timer_set_next_event; - ce->set_state_shutdown = rk_timer_shutdown; - ce->set_state_periodic = rk_timer_set_periodic; ce->irq = irq; ce->cpumask = cpu_all_mask; ce->rating = 250; @@ -177,4 +224,27 @@ out_unmap: iounmap(bc_timer.base); } -CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init); +static void __init rk_timer_v1_init(struct device_node *np) +{ + struct clock_event_device *ce = &bc_timer.ce; + + ce->set_next_event = rk_timer_v1_set_next_event; + ce->set_state_shutdown = rk_timer_v1_shutdown; + ce->set_state_periodic = rk_timer_v1_set_periodic; + + rk_timer_init(np, rk_timer_v1_interrupt); +} + +static void __init rk_timer_v2_init(struct device_node *np) +{ + struct clock_event_device *ce = &bc_timer.ce; + + ce->set_next_event = rk_timer_v2_set_next_event; + ce->set_state_shutdown = rk_timer_v2_shutdown; + ce->set_state_periodic = rk_timer_v2_set_periodic; + + rk_timer_init(np, rk_timer_v2_interrupt); +} + +CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_v1_init); +CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_v2_init);