diff mbox

arm64: fix the wrong comment

Message ID 1464574369-22618-1-git-send-email-shijie.huang@arm.com (mailing list archive)
State New, archived
Headers show

Commit Message

Huang Shijie May 30, 2016, 2:12 a.m. UTC 
Currently, we use the 48-bit for the kernel and user by default.
The comment becomes stale. This patch fixes the wrong comment.

Signed-off-by: Huang Shijie <shijie.huang@arm.com>
---
 arch/arm64/mm/proc.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Will Deacon June 2, 2016, 6:09 p.m. UTC | #1 
On Mon, May 30, 2016 at 10:12:49AM +0800, Huang Shijie wrote:
> Currently, we use the 48-bit for the kernel and user by default.
> The comment becomes stale. This patch fixes the wrong comment.
> 
> Signed-off-by: Huang Shijie <shijie.huang@arm.com>
> ---
>  arch/arm64/mm/proc.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index c431787..421386759 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -209,8 +209,8 @@ ENTRY(__cpu_setup)
>  	bic	x0, x0, x5			// clear bits
>  	orr	x0, x0, x6			// set bits
>  	/*
> -	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
> -	 * both user and kernel.
> +	 * Set/prepare TCR. We use VA_BITS of address range for both
> +	 * kernel and user.
>  	 */

To be honest, all three of these comments (including the two in the
context) are totally useless. Can we just remove them instead?

Will
diff mbox

Patch

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index c431787..421386759 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -209,8 +209,8 @@  ENTRY(__cpu_setup)
 	bic	x0, x0, x5			// clear bits
 	orr	x0, x0, x6			// set bits
 	/*
-	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
-	 * both user and kernel.
+	 * Set/prepare TCR. We use VA_BITS of address range for both
+	 * kernel and user.
 	 */
 	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
 			TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0