| Message ID | 1465216900-11755-5-git-send-email-pramod.kumar@broadcom.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 06/06/2016 05:41 AM, Pramod Kumar wrote: > Add integrated MDIO multiplexer driver node which contains > two mux PCIe bus and one ethernet bus along with phys > lying on these bus. > > Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> > --- > + mdio_mux_iproc: mdio-mux@6602023c { > + compatible = "brcm,mdio-mux-iproc"; > + reg = <0x6602023c 0x14>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + mdio@0 { > + reg = <0x0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + pci_phy0: pci-phy@0 { > + compatible = "brcm,ns2-pcie-phy"; > + reg = <0x0>; > + #phy-cells = <0>; > + }; > + }; > + > + mdio@7 { > + reg = <0x7>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + pci_phy1: pci-phy@0 { > + compatible = "brcm,ns2-pcie-phy"; > + reg = <0x0>; > + #phy-cells = <0>; > + }; Are these two PHYs always available in the NS2 SoC, or does that depend on interfaces exposed at the board level? Should not they be flagged with a disabled status property by default and enabled in their respective board files?
Hi Florian, > -----Original Message----- > From: Florian Fainelli [mailto:f.fainelli@gmail.com] > Sent: 07 June 2016 00:08 > To: Pramod Kumar; Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell; > Kumar Gala; Catalin Marinas; Will Deacon; Kishon Vijay Abraham I; David S. > Miller > Cc: devicetree@vger.kernel.org; netdev@vger.kernel.org; linux- > kernel@vger.kernel.org; bcm-kernel-feedback-list@broadcom.com; linux-arm- > kernel@lists.infradead.org > Subject: Re: [PATCH v4 4/7] dt: mdio-mux: Add mdio multiplexer driver node > > On 06/06/2016 05:41 AM, Pramod Kumar wrote: > > Add integrated MDIO multiplexer driver node which contains two mux > > PCIe bus and one ethernet bus along with phys lying on these bus. > > > > Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> > > --- > > + mdio_mux_iproc: mdio-mux@6602023c { > > + compatible = "brcm,mdio-mux-iproc"; > > + reg = <0x6602023c 0x14>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + mdio@0 { > > + reg = <0x0>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + pci_phy0: pci-phy@0 { > > + compatible = "brcm,ns2-pcie-phy"; > > + reg = <0x0>; > > + #phy-cells = <0>; > > + }; > > + }; > > + > > + mdio@7 { > > + reg = <0x7>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + pci_phy1: pci-phy@0 { > > + compatible = "brcm,ns2-pcie-phy"; > > + reg = <0x0>; > > + #phy-cells = <0>; > > + }; > > Are these two PHYs always available in the NS2 SoC, or does that depend on > interfaces exposed at the board level? Should not they be flagged with a > disabled status property by default and enabled in their respective board > files? > -- It depends on the interfaces exposed at board level. We will disable it in dtsi and enable it dts file. I'll address this through next patch set. > Florian Regards, Pramod
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index 54ca40c..71f8503 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -132,3 +132,15 @@ #size-cells = <1>; }; }; + +&mdio_mux_iproc { + mdio@10 { + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + + gphy0: eth-phy@10 { + reg = <0x10>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index ec68ec1..9f20a66 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -263,6 +263,37 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + mdio_mux_iproc: mdio-mux@6602023c { + compatible = "brcm,mdio-mux-iproc"; + reg = <0x6602023c 0x14>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + pci_phy0: pci-phy@0 { + compatible = "brcm,ns2-pcie-phy"; + reg = <0x0>; + #phy-cells = <0>; + }; + }; + + mdio@7 { + reg = <0x7>; + #address-cells = <1>; + #size-cells = <0>; + + pci_phy1: pci-phy@0 { + compatible = "brcm,ns2-pcie-phy"; + reg = <0x0>; + #phy-cells = <0>; + }; + }; + }; + timer0: timer@66030000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x66030000 0x1000>;
Add integrated MDIO multiplexer driver node which contains two mux PCIe bus and one ethernet bus along with phys lying on these bus. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> --- arch/arm64/boot/dts/broadcom/ns2-svk.dts | 12 ++++++++++++ arch/arm64/boot/dts/broadcom/ns2.dtsi | 31 +++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)