From patchwork Tue Jun 7 04:54:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 9159851 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F3A9B60467 for ; Tue, 7 Jun 2016 04:57:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E8DBC26861 for ; Tue, 7 Jun 2016 04:57:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DD9022833E; Tue, 7 Jun 2016 04:57:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9715F26861 for ; Tue, 7 Jun 2016 04:57:03 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bA93B-0003Mg-3i; Tue, 07 Jun 2016 04:55:37 +0000 Received: from mail-pa0-f66.google.com ([209.85.220.66]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1bA92t-00020M-QT; Tue, 07 Jun 2016 04:55:21 +0000 Received: by mail-pa0-f66.google.com with SMTP id gp3so13246024pac.2; Mon, 06 Jun 2016 21:54:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=z70OtIkcSPj5Uay5QgTQZF+s9z1K+/dTUJUvLo2V39c=; b=ILuq7NBmNsKprFyXWiMn2k5/4SB6C5LSE3oa4PAwnKgzQXDkbaJSomIwvmuzqsBHqk +kOrARPt2+kkoN6HfFix9ROQQ9ZliUj28/6hNhbUmcqw3bbUdDVOfbN674gpMH5FlVRG iPvUC4qzCxsNzplgzwNuMvextdZ0i0VkrWAKbexQdsB/QCu52nQ5yEytbT0Sw1mPcf7A 4XzCL7HQljs/iG25tN1dnLUaSsQ1vmV40kcIIEfkeqo5dpgfl8DAPYr9S9Bm6RTwGn0C owE4OFvlALWQ5x2u6CB9e2ZdvGpZEj1avl9RL4OvHGVijZoN1faZ7GUlPIqp2rJB0rCE AdXQ== X-Gm-Message-State: ALyK8tLUy4q8/kaZiGCNXYDMW4J5bDRvFEMo2kKulYLuWh02IOd+1n7vn1WVLxe9640oUA== X-Received: by 10.66.216.202 with SMTP id os10mr28512769pac.91.1465275298831; Mon, 06 Jun 2016 21:54:58 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id kb15sm29074009pad.28.2016.06.06.21.54.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 06 Jun 2016 21:54:58 -0700 (PDT) From: Caesar Wang To: daniel.lezcano@linaro.org, Heiko Stuebner Subject: [PATCH v2 3/4] clocksource: rockchip: add support for rk3399 SoC Date: Tue, 7 Jun 2016 12:54:32 +0800 Message-Id: <1465275273-22076-4-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465275273-22076-1-git-send-email-wxt@rock-chips.com> References: <1465275273-22076-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160606_215520_181732_0C1E6547 X-CRM114-Status: GOOD ( 13.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangtao@rock-chips.com, dianders@chromium.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, smbarber@google.com, cf@rock-chips.com, briannorris@google.com, Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Caesar Wang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Huang, Tao" The CONTROL register offset is different from old SoCs. For Linux driver, there are not functional changes at all. So add dedicated mapping for the CONTROL register. Signed-off-by: Huang Tao Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Heiko Stuebner Tested-by: Jianqun Xu Signed-off-by: Caesar Wang --- Changes in v2: - As the Daniel suggests on https://patchwork.kernel.org/patch/9135061/, That will be better for the rockchip timer driver. drivers/clocksource/rockchip_timer.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c index b510863..a3f22b0 100644 --- a/drivers/clocksource/rockchip_timer.c +++ b/drivers/clocksource/rockchip_timer.c @@ -19,7 +19,8 @@ #define TIMER_LOAD_COUNT0 0x00 #define TIMER_LOAD_COUNT1 0x04 -#define TIMER_CONTROL_REG 0x10 +#define TIMER_CONTROL_REG3288 0x10 +#define TIMER_CONTROL_REG3399 0x1c #define TIMER_INT_STATUS 0x18 #define TIMER_DISABLE 0x0 @@ -31,6 +32,7 @@ struct bc_timer { struct clock_event_device ce; void __iomem *base; + void __iomem *ctrl; u32 freq; }; @@ -46,15 +48,20 @@ static inline void __iomem *rk_base(struct clock_event_device *ce) return rk_timer(ce)->base; } +static inline void __iomem *rk_ctrl(struct clock_event_device *ce) +{ + return rk_timer(ce)->ctrl; +} + static inline void rk_timer_disable(struct clock_event_device *ce) { - writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG); + writel_relaxed(TIMER_DISABLE, rk_ctrl(ce)); } static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags) { writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags, - rk_base(ce) + TIMER_CONTROL_REG); + rk_ctrl(ce)); } static void rk_timer_update_counter(unsigned long cycles, @@ -106,7 +113,7 @@ static irqreturn_t rk_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static void __init rk_timer_init(struct device_node *np) +static void __init rk_timer_init(struct device_node *np, u32 ctrl_reg) { struct clock_event_device *ce = &bc_timer.ce; struct clk *timer_clk; @@ -118,6 +125,7 @@ static void __init rk_timer_init(struct device_node *np) pr_err("Failed to get base address for '%s'\n", TIMER_NAME); return; } + bc_timer.ctrl = bc_timer.base + ctrl_reg; pclk = of_clk_get_by_name(np, "pclk"); if (IS_ERR(pclk)) { @@ -180,4 +188,17 @@ out_unmap: iounmap(bc_timer.base); } -CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init); +static void __init rk3288_timer_init(struct device_node *np) +{ + rk_timer_init(np, TIMER_CONTROL_REG3288); +} + +static void __init rk3399_timer_init(struct device_node *np) +{ + rk_timer_init(np, TIMER_CONTROL_REG3399); +} + +CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", + rk3288_timer_init); +CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", + rk3399_timer_init);