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[213.113.124.204]) by smtp.gmail.com with ESMTPSA id e32sm2266067lji.41.2016.06.14.08.31.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Jun 2016 08:31:18 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Andy Gross Subject: [PATCH 2/5] ARM: dts: add SDCC5 to Qualcomm MSM8660 Date: Tue, 14 Jun 2016 17:30:56 +0200 Message-Id: <1465918259-11138-3-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1465918259-11138-1-git-send-email-linus.walleij@linaro.org> References: <1465918259-11138-1-git-send-email-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160614_083143_116838_2E700175 X-CRM114-Status: GOOD ( 11.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Brown , Linus Walleij , Stephen Boyd , Bjorn Andersson MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The SDCC5 SD/MMC controller is used for a second uSD slot on the APQ8060 Dragonboard. On most other systems it is just dark silicon so define it and leave it as "disabled" in the core SoC file. Signed-off-by: Linus Walleij Reviewed-by: Stephen Boyd --- arch/arm/boot/dts/qcom-msm8660.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 6a62b62ad980..a5a38820554a 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -262,6 +262,22 @@ no-1-8-v; vmmc-supply = <&vsdcc_fixed>; }; + + sdcc5: sdcc@12200000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12200000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + vmmc-supply = <&vsdcc_fixed>; + }; }; tcsr: syscon@1a400000 {