From patchwork Mon Jun 27 13:09:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylvain Lemieux X-Patchwork-Id: 9200543 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 52DC4607D3 for ; Mon, 27 Jun 2016 13:12:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 457C32858D for ; Mon, 27 Jun 2016 13:12:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 38ED628594; Mon, 27 Jun 2016 13:12:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_WEB, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 142652858D for ; Mon, 27 Jun 2016 13:12:05 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bHWJN-0003nA-UR; Mon, 27 Jun 2016 13:10:49 +0000 Received: from mail-it0-x242.google.com ([2607:f8b0:4001:c0b::242]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bHWJ2-0003GN-3P for linux-arm-kernel@lists.infradead.org; Mon, 27 Jun 2016 13:10:29 +0000 Received: by mail-it0-x242.google.com with SMTP id f6so10093285ith.1 for ; Mon, 27 Jun 2016 06:10:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Jxm4Rj0OStNvZN20A7SJ1qN+fpiCU7CEFxnjtmHKYZw=; b=tuszucUoq52jpGBJtyzVcBpMsGnoD2oPcgVVDWLOlILLS9VLhl+6lVwedMjL3HzFK1 TDeWeO+QLhfSrc7n8xplIwc4bH+FtwkpQ7T12vUTkKV5o1fJ5ZhT3a6UyUd0hDDawN0G nytEoKASn2QfijSq0LZ8K6ZsLCol954nLX/o2EjuPirfc/h2o+L7V3IOW/PIUkvPpmVr HPSbhv/YHPAG6aHl6VXs+aSD4Pzum+ydrapnQZlevsCd09y8BBqWL9zR8TIcZsqk8jgA VLEpk4k2qfyNH5ID4v5JmXExuMvVQVsUcNns8wCn3dJVqvF06Od7Bqma+YuHw+qY82wT AR7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jxm4Rj0OStNvZN20A7SJ1qN+fpiCU7CEFxnjtmHKYZw=; b=O292ZThkjv5vKJxJ0fSnvnBa4ETQoDBs4+96vKIadLCXE21NyCpAysGFhlGvFsOQvM EzwtAkD1RitxCb7zul+aNmecW2Uwy0Puzvq9S/WklskG1sR+8ex13IyhO1vj0loF0qPt BmBenCN54nYKOfSqAgNsyh2ypFp+wBArka+vO2NHahxnA7IPGBAkLuRvjoedzIba81TQ swZsNCtoR1SFhyY9UFPFUfbalHhKMhz/19SxqKvYDv9wqeGWyUkq3+h0dJ9a/PYpzyJm K+yAJ8PhuWp7qPBqZq+GIDzMh4j2z99i6PAFy3TjaUnWMyygODL+6ofWnlYOEWkMmBYp wFpQ== X-Gm-Message-State: ALyK8tLFhaMl/BwQhzO+BM4pSnJXb2s2mXHXfnUAxVN58TL0y8EvyE2LghJmrKipC1db+w== X-Received: by 10.36.192.9 with SMTP id u9mr8825621itf.90.1467033007136; Mon, 27 Jun 2016 06:10:07 -0700 (PDT) Received: from CABRO3AP00510.americas.tsp.ad ([74.51.240.241]) by smtp.gmail.com with ESMTPSA id w101sm9365919ioi.12.2016.06.27.06.10.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Jun 2016 06:10:06 -0700 (PDT) From: Sylvain Lemieux To: vz@mleia.com, thierry.reding@gmail.com Subject: [PATCH v2 2/3] pwm: lpc32xx: Add support for PWM_PIN_LEVEL bit configuration Date: Mon, 27 Jun 2016 09:09:56 -0400 Message-Id: <1467032997-5340-3-git-send-email-slemieux.tyco@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1467032997-5340-1-git-send-email-slemieux.tyco@gmail.com> References: <1467032997-5340-1-git-send-email-slemieux.tyco@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160627_061028_249033_113171E0 X-CRM114-Status: GOOD ( 13.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sylvain Lemieux Provide support to configure the pin output (i.e. PWM_PIN_LEVEL bit) when the PWM is disabled. Note: When the LPC32xx PWM is disabled, both options of pin output high and low level values are valid; however this particular controller does not have polarity control. Refer to the LPC32x0 User Manual [1], for details. [1] http://www.nxp.com/documents/user_manual/UM10326.pdf Signed-off-by: Sylvain Lemieux --- Changes from v1 to v2: * New patch in version 2. drivers/pwm/pwm-lpc32xx.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index a9b3cff..d1bd901 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -130,9 +130,13 @@ static int lpc32xx_pwm_probe(struct platform_device *pdev) return ret; } - /* When PWM is disable, configure the output to the default value */ + /* When PWM is disable, configure the output correctly */ val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); - val &= ~PWM_PIN_LEVEL; + if (device_property_read_bool(&pdev->dev, + "nxp,pwm-disabled-level-high")) + val |= PWM_PIN_LEVEL; + else + val &= ~PWM_PIN_LEVEL; writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); platform_set_drvdata(pdev, lpc32xx);