diff mbox

[2/2] arm64: dts: r8a7795: add FDP1 device nodes

Message ID 1467293563-940-3-git-send-email-kieran@bingham.xyz (mailing list archive)
State New, archived
Headers show

Commit Message

Kieran Bingham June 30, 2016, 1:32 p.m. UTC 
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran@bingham.xyz>
--
changes for v2
 - channel labels dropped

 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

Comments

Kieran Bingham July 1, 2016, 2:37 p.m. UTC | #1 
Hi Simon,

The bindings for this have now been acked by RobH.

--
Cheers

Kieran

On 30/06/16 14:32, Kieran Bingham wrote:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Kieran Bingham <kieran@bingham.xyz>
> --
> changes for v2
>  - channel labels dropped
> 
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index a451bd217f05..8bc87e09efd7 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -1443,5 +1443,32 @@
>  			clocks = <&cpg CPG_MOD 613>;
>  			power-domains = <&sysc R8A7795_PD_A3VP>;
>  		};
> +
> +		fdp1@fe940000 {
> +			compatible = "renesas,fdp1";
> +			reg = <0 0xfe940000 0 0x2400>;
> +			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 119>;
> +			power-domains = <&sysc R8A7795_PD_A3VP>;
> +			renesas,fcp = <&fcpf0>;
> +		};
> +
> +		fdp1@fe944000 {
> +			compatible = "renesas,fdp1";
> +			reg = <0 0xfe944000 0 0x2400>;
> +			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 118>;
> +			power-domains = <&sysc R8A7795_PD_A3VP>;
> +			renesas,fcp = <&fcpf1>;
> +		};
> +
> +		fdp1@fe948000 {
> +			compatible = "renesas,fdp1";
> +			reg = <0 0xfe948000 0 0x2400>;
> +			interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 117>;
> +			power-domains = <&sysc R8A7795_PD_A3VP>;
> +			renesas,fcp = <&fcpf2>;
> +		};
>  	};
>  };
>
Simon Horman July 4, 2016, 12:45 p.m. UTC | #2 
On Fri, Jul 01, 2016 at 03:37:23PM +0100, Kieran Bingham wrote:
> Hi Simon,
> 
> The bindings for this have now been acked by RobH.

Thanks, I have queued these up for v4.9.

There was a small amount of fuzz when applying the first patch,
please check to make sure it has been applied correctly once
it hits the devel branch of the renesas tree.
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index a451bd217f05..8bc87e09efd7 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1443,5 +1443,32 @@ 
 			clocks = <&cpg CPG_MOD 613>;
 			power-domains = <&sysc R8A7795_PD_A3VP>;
 		};
+
+		fdp1@fe940000 {
+			compatible = "renesas,fdp1";
+			reg = <0 0xfe940000 0 0x2400>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 119>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+			renesas,fcp = <&fcpf0>;
+		};
+
+		fdp1@fe944000 {
+			compatible = "renesas,fdp1";
+			reg = <0 0xfe944000 0 0x2400>;
+			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 118>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+			renesas,fcp = <&fcpf1>;
+		};
+
+		fdp1@fe948000 {
+			compatible = "renesas,fdp1";
+			reg = <0 0xfe948000 0 0x2400>;
+			interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 117>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+			renesas,fcp = <&fcpf2>;
+		};
 	};
 };