From patchwork Tue Jul 5 06:00:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yendapally Reddy Dhananjaya Reddy X-Patchwork-Id: 9213695 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4C62F6048B for ; Tue, 5 Jul 2016 06:02:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3CEC3288D2 for ; Tue, 5 Jul 2016 06:02:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3167A288D4; Tue, 5 Jul 2016 06:02:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 91293288D2 for ; Tue, 5 Jul 2016 06:02:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bKJQM-0002p1-Aw; Tue, 05 Jul 2016 06:01:34 +0000 Received: from mail-pf0-x231.google.com ([2607:f8b0:400e:c00::231]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bKJQ9-0002fg-Q1 for linux-arm-kernel@lists.infradead.org; Tue, 05 Jul 2016 06:01:23 +0000 Received: by mail-pf0-x231.google.com with SMTP id i123so66950647pfg.0 for ; Mon, 04 Jul 2016 23:01:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bxX8BeQyKIF8xmBpTESvvZRyvwOm2BFEUdUKSDAGHh4=; b=DmW/kPZ9QMP8vYHNLxuNIz/0ldIzz2Qlym9UWCglsucwFscE13xkFIbWCiR6TU+V6y qWSbHKbyzKdRLV6ufq6v45T+QpyG8y8ESgetIiHiLfcIhvcknsXHYXJgkrePGVeVNGoD AqTuB8NemvLdRxriGLcGGxoUye8dZdq5rTbk0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bxX8BeQyKIF8xmBpTESvvZRyvwOm2BFEUdUKSDAGHh4=; b=gOgJ8uI431578LE1Mjza2F5p9Susn25tTBCCjfIaKtHUW6TzQa8kwKoQyceyZqJjFx Gd8A0CCxVa7gHd52vUPyGu/woVSHAhJlbYcWNhHe+J1hvXRBYv6T1oJbY5ozcqjjnFLB ZxdMe0LNCE0RT+dfp8RTaxHIET/KuOXtwzM8y7/6l1zcNKVJCvRoKTKYKCbrDm2BYBFB YxTxxBv3rr6BMKIxEKkE8cW4ex4jDYBNRg7otQ337lMb7YMXU0Rd8L0X7eTsc+HOu4zX 9Is2ZPzb5bqrwcM0nfGMONYpGOJLInyZZThmpKHQ4wvFHP3gV9P2mhaWvMxDfEFCjiWO Rb+Q== X-Gm-Message-State: ALyK8tIGfvO+3MoVi5IGdiIzbU68AYeeAt9RAE2ZHHv6KuzbnprQ2z7YOvYEN5/Bxm4eOwgs X-Received: by 10.98.62.15 with SMTP id l15mr29434071pfa.24.1467698455235; Mon, 04 Jul 2016 23:00:55 -0700 (PDT) Received: from xl-rtp-02.rtp.broadcom.com ([216.31.219.19]) by smtp.gmail.com with ESMTPSA id e126sm1517440pfc.5.2016.07.04.23.00.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jul 2016 23:00:54 -0700 (PDT) From: Yendapally Reddy Dhananjaya Reddy To: Thierry Reding , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Ray Jui , Scott Branden , Jon Mason , Russell King Subject: [PATCH v5 2/3] pwm: iproc: Add support for Broadcom iproc pwm controller Date: Tue, 5 Jul 2016 02:00:25 -0400 Message-Id: <1467698426-27600-3-git-send-email-yendapally.reddy@broadcom.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1467698426-27600-1-git-send-email-yendapally.reddy@broadcom.com> References: <1467698426-27600-1-git-send-email-yendapally.reddy@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160704_230122_067378_4A4A0CB2 X-CRM114-Status: GOOD ( 24.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yendapally Reddy Dhananjaya Reddy , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the PWM controller present in Broadcom's iProc family of SoCs.It has been tested on the Northstar+ bcm958625HR board. Signed-off-by: Yendapally Reddy Dhananjaya Reddy --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-bcm-iproc.c | 268 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 279 insertions(+) create mode 100644 drivers/pwm/pwm-bcm-iproc.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index c182efc..1339b62 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -74,6 +74,16 @@ config PWM_ATMEL_TCB To compile this driver as a module, choose M here: the module will be called pwm-atmel-tcb. +config PWM_BCM_IPROC + tristate "iProc PWM support" + depends on ARCH_BCM_IPROC || COMPILE_TEST + help + Generic PWM framework driver for Broadcom iProc PWM block. This + block is used in Broadcom iProc SoC's. + + To compile this driver as a module, choose M here: the module + will be called pwm-bcm-iproc. + config PWM_BCM_KONA tristate "Kona PWM support" depends on ARCH_BCM_MOBILE diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index dd35bc1..a196d79 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o +obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o obj-$(CONFIG_PWM_BERLIN) += pwm-berlin.o diff --git a/drivers/pwm/pwm-bcm-iproc.c b/drivers/pwm/pwm-bcm-iproc.c new file mode 100644 index 0000000..aff260c --- /dev/null +++ b/drivers/pwm/pwm-bcm-iproc.c @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2016 Broadcom + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IPROC_PWM_CTRL_OFFSET (0x00) +#define IPROC_PWM_CTRL_TYPE_SHIFT(chan) (15 + (chan)) +#define IPROC_PWM_CTRL_POLARITY_SHIFT(chan) (8 + (chan)) +#define IPROC_PWM_CTRL_EN_SHIFT(chan) (chan) + +#define IPROC_PWM_PERIOD_OFFSET(chan) (0x04 + ((chan) << 3)) +#define IPROC_PWM_PERIOD_MIN (0x02) +#define IPROC_PWM_PERIOD_MAX (0xffff) + +#define IPROC_PWM_DUTY_CYCLE_OFFSET(chan) (0x08 + ((chan) << 3)) +#define IPROC_PWM_DUTY_CYCLE_MIN (0x00) +#define IPROC_PWM_DUTY_CYCLE_MAX (0xffff) + +#define IPROC_PWM_PRESCALE_OFFSET (0x24) +#define IPROC_PWM_PRESCALE_BITS (0x06) +#define IPROC_PWM_PRESCALE_SHIFT(chan) ((3 - (chan)) * \ + IPROC_PWM_PRESCALE_BITS) +#define IPROC_PWM_PRESCALE_MASK(chan) (IPROC_PWM_PRESCALE_MAX << \ + IPROC_PWM_PRESCALE_SHIFT(chan)) +#define IPROC_PWM_PRESCALE_MIN (0x00) +#define IPROC_PWM_PRESCALE_MAX (0x3f) + +#define IPROC_PWM_CHANNEL_COUNT (0x04) + +struct iproc_pwmc { + struct pwm_chip chip; + void __iomem *base; + struct clk *clk; +}; + +static inline struct iproc_pwmc *to_iproc_pwmc(struct pwm_chip *_chip) +{ + return container_of(_chip, struct iproc_pwmc, chip); +} + +static void iproc_pwmc_enable(struct iproc_pwmc *ip, u32 chan, bool set) +{ + unsigned int value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); + + if (set) + value |= 1 << IPROC_PWM_CTRL_EN_SHIFT(chan); + else + value &= ~(1 << IPROC_PWM_CTRL_EN_SHIFT(chan)); + writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); + + /* must be a min 400ns delay between clearing and setting enable bit. */ + ndelay(400); +} + +void iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct iproc_pwmc *ip = to_iproc_pwmc(chip); + u32 chan = pwm->hwpwm; + u64 val, multi, rate; + u32 reg_data; + u32 prescale; + + rate = clk_get_rate(ip->clk); + + reg_data = readl(ip->base + IPROC_PWM_CTRL_OFFSET); + if (reg_data & BIT(IPROC_PWM_CTRL_EN_SHIFT(chan))) + state->enabled = true; + else + state->enabled = false; + + if (reg_data & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(chan))) + state->polarity = PWM_POLARITY_NORMAL; + else + state->polarity = PWM_POLARITY_INVERSED; + + reg_data = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET); + prescale = reg_data >> IPROC_PWM_PRESCALE_SHIFT(chan); + prescale &= IPROC_PWM_PRESCALE_MAX; + + multi = 1000000000; + + reg_data = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(chan)); + val = (reg_data & IPROC_PWM_PERIOD_MAX) * (prescale + 1) * multi; + val = div64_u64(val, rate); + state->period = val; + + reg_data = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(chan)); + val = (reg_data & IPROC_PWM_PERIOD_MAX) * (prescale + 1) * multi; + val = div64_u64(val, rate); + state->duty_cycle = val; +} + +static int iproc_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + unsigned long prescale = IPROC_PWM_PRESCALE_MIN; + struct iproc_pwmc *ip = to_iproc_pwmc(chip); + unsigned int reg_data, chan = pwm->hwpwm; + unsigned long period_cnt, duty_cnt; + u64 val, div, rate; + + rate = clk_get_rate(ip->clk); + + /* + * Find period count, duty count and prescale to suit duty_cycle and + * period. This is done according to formulas described below: + * + * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE + * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE + * + * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1)) + * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1)) + */ + while (1) { + div = 1000000000; + div *= 1 + prescale; + val = rate * state->period; + period_cnt = div64_u64(val, div); + val = rate * state->duty_cycle; + duty_cnt = div64_u64(val, div); + + if (period_cnt < IPROC_PWM_PERIOD_MIN || + duty_cnt < IPROC_PWM_DUTY_CYCLE_MIN) + return -EINVAL; + + if (period_cnt <= IPROC_PWM_PERIOD_MAX && + duty_cnt <= IPROC_PWM_DUTY_CYCLE_MAX) + break; + + /* Otherwise, increase prescale and recalculate counts */ + if (++prescale > IPROC_PWM_PRESCALE_MAX) + return -EINVAL; + } + + iproc_pwmc_enable(ip, chan, false); + + /* Set prescale */ + reg_data = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET); + reg_data &= ~IPROC_PWM_PRESCALE_MASK(chan); + reg_data |= prescale << IPROC_PWM_PRESCALE_SHIFT(chan); + writel(reg_data, ip->base + IPROC_PWM_PRESCALE_OFFSET); + + /* set period and duty cycle */ + writel(period_cnt, ip->base + IPROC_PWM_PERIOD_OFFSET(chan)); + writel(duty_cnt, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(chan)); + + /* set polarity */ + reg_data = readl(ip->base + IPROC_PWM_CTRL_OFFSET); + if (state->polarity == PWM_POLARITY_NORMAL) + reg_data |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(chan); + else + reg_data &= ~(1 << IPROC_PWM_CTRL_POLARITY_SHIFT(chan)); + writel(reg_data, ip->base + IPROC_PWM_CTRL_OFFSET); + + if (state->enabled) + iproc_pwmc_enable(ip, chan, true); + + return 0; +} + +static const struct pwm_ops iproc_pwm_ops = { + .apply = iproc_pwmc_apply, + .get_state = iproc_pwmc_get_state, +}; + +static int iproc_pwmc_probe(struct platform_device *pdev) +{ + struct iproc_pwmc *ip; + struct resource *res; + unsigned int value; + unsigned int chan; + int ret; + + ip = devm_kzalloc(&pdev->dev, sizeof(*ip), GFP_KERNEL); + if (ip == NULL) + return -ENOMEM; + + platform_set_drvdata(pdev, ip); + + ip->chip.dev = &pdev->dev; + ip->chip.ops = &iproc_pwm_ops; + ip->chip.base = -1; + ip->chip.npwm = IPROC_PWM_CHANNEL_COUNT; + ip->chip.of_xlate = of_pwm_xlate_with_flags; + ip->chip.of_pwm_n_cells = 3; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ip->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ip->base)) + return PTR_ERR(ip->base); + + ip->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(ip->clk)) { + dev_err(&pdev->dev, "failed to get clock: %ld\n", + PTR_ERR(ip->clk)); + return PTR_ERR(ip->clk); + } + + ret = clk_prepare_enable(ip->clk); + if (ret < 0) { + dev_err(&pdev->dev, "failed to enable clock: %d\n", ret); + return ret; + } + + /* Set full drive and normal polarity for all channels */ + value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); + for (chan = 0; chan < ip->chip.npwm; chan++) { + value &= ~(1 << IPROC_PWM_CTRL_TYPE_SHIFT(chan)); + value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(chan); + } + writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); + + ret = pwmchip_add(&ip->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); + clk_disable_unprepare(ip->clk); + } + + return ret; +} + +static int iproc_pwmc_remove(struct platform_device *pdev) +{ + struct iproc_pwmc *ip = platform_get_drvdata(pdev); + + clk_disable_unprepare(ip->clk); + + return pwmchip_remove(&ip->chip); +} + +static const struct of_device_id bcm_iproc_pwmc_dt[] = { + { .compatible = "brcm,iproc-pwm" }, + { }, +}; +MODULE_DEVICE_TABLE(of, bcm_iproc_pwmc_dt); + +static struct platform_driver iproc_pwmc_driver = { + .driver = { + .name = "bcm-iproc-pwm", + .of_match_table = bcm_iproc_pwmc_dt, + }, + .probe = iproc_pwmc_probe, + .remove = iproc_pwmc_remove, +}; +module_platform_driver(iproc_pwmc_driver); + +MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy "); +MODULE_DESCRIPTION("Broadcom iProc PWM driver"); +MODULE_LICENSE("GPL v2");