From patchwork Tue Jul 5 20:19:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 9215185 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 27BDD6048B for ; Tue, 5 Jul 2016 20:22:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 195172840B for ; Tue, 5 Jul 2016 20:22:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0DCE72840D; Tue, 5 Jul 2016 20:22:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B68662840B for ; Tue, 5 Jul 2016 20:22:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bKWpn-0001nY-7z; Tue, 05 Jul 2016 20:20:43 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bKWpg-0001iV-T3 for linux-arm-kernel@lists.infradead.org; Tue, 05 Jul 2016 20:20:38 +0000 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1bKWp3-0000Id-0K; Tue, 05 Jul 2016 22:19:57 +0200 Received: from ukl by dude.hi.pengutronix.de with local (Exim 4.87) (envelope-from ) id 1bKWp0-0003nE-He; Tue, 05 Jul 2016 22:19:54 +0200 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= To: Shawn Guo , kernel@pengutronix.de Subject: [PATCH 2/3] ARM: dts: imx25: don't configure reserved pad settings Date: Tue, 5 Jul 2016 22:19:52 +0200 Message-Id: <1467749993-14533-3-git-send-email-u.kleine-koenig@pengutronix.de> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1467749993-14533-1-git-send-email-u.kleine-koenig@pengutronix.de> References: <1467749993-14533-1-git-send-email-u.kleine-koenig@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160705_132037_265564_F6FF8276 X-CRM114-Status: UNSURE ( 9.70 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fabio Estevam , linux-arm-kernel@lists.infradead.org, Stefan Agner , =?UTF-8?q?Andreas=20F=C3=A4rber?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Two dts files specified reserved bits in their pad setting value for some pins. This commit just unsets the reserved bits, which matches the hardware behaviour when writing a 1 to a reserved bit. Signed-off-by: Uwe Kleine-König --- .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 24 +++++++++++----------- arch/arm/boot/dts/imx25-pdk.dts | 16 +++++++-------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index 9efcdad20e73..1a4b08df061c 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -78,10 +78,10 @@ &iomuxc { pinctrl_audmux: audmuxgrp { fsl,pins = < - MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 - MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 - MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 - MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 + MX25_PAD_KPP_COL3__AUD5_TXFS 0x000000a0 + MX25_PAD_KPP_COL2__AUD5_TXC 0x000000a0 + MX25_PAD_KPP_COL1__AUD5_RXD 0x000000a0 + MX25_PAD_KPP_COL0__AUD5_TXD 0x000000a0 >; }; @@ -106,10 +106,10 @@ pinctrl_lcdc: lcdcgrp { fsl,pins = < - MX25_PAD_LD0__LD0 0x1 - MX25_PAD_LD1__LD1 0x1 + MX25_PAD_LD0__LD0 0x0 + MX25_PAD_LD1__LD1 0x0 MX25_PAD_LD2__LD2 0x1 - MX25_PAD_LD3__LD3 0x1 + MX25_PAD_LD3__LD3 0x0 MX25_PAD_LD4__LD4 0x1 MX25_PAD_LD5__LD5 0x1 MX25_PAD_LD6__LD6 0x1 @@ -120,10 +120,10 @@ MX25_PAD_LD11__LD11 0x1 MX25_PAD_LD12__LD12 0x1 MX25_PAD_LD13__LD13 0x1 - MX25_PAD_LD14__LD14 0x1 - MX25_PAD_LD15__LD15 0x1 - MX25_PAD_GPIO_E__LD16 0x1 - MX25_PAD_GPIO_F__LD17 0x1 + MX25_PAD_LD14__LD14 0x0 + MX25_PAD_LD15__LD15 0x0 + MX25_PAD_GPIO_E__LD16 0x0 + MX25_PAD_GPIO_F__LD17 0x0 MX25_PAD_HSYNC__HSYNC 0x80000000 MX25_PAD_VSYNC__VSYNC 0x80000000 MX25_PAD_LSCLK__LSCLK 0x80000000 @@ -137,7 +137,7 @@ MX25_PAD_UART1_RTS__UART1_RTS 0xe0 MX25_PAD_UART1_CTS__UART1_CTS 0xe0 MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + MX25_PAD_UART1_RXD__UART1_RXD 0x00000080 >; }; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 8b00cfca18ea..c823e45a7a01 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -147,10 +147,10 @@ &iomuxc { pinctrl_audmux: audmuxgrp { fsl,pins = < - MX25_PAD_RW__AUD4_TXFS 0xe0 - MX25_PAD_OE__AUD4_TXC 0xe0 - MX25_PAD_EB0__AUD4_TXD 0xe0 - MX25_PAD_EB1__AUD4_RXD 0xe0 + MX25_PAD_RW__AUD4_TXFS 0x80 + MX25_PAD_OE__AUD4_TXC 0x80 + MX25_PAD_EB0__AUD4_TXD 0x80 + MX25_PAD_EB1__AUD4_RXD 0x80 >; }; @@ -227,10 +227,10 @@ MX25_PAD_LD11__LD11 0xe0 MX25_PAD_LD12__LD12 0xe0 MX25_PAD_LD13__LD13 0xe0 - MX25_PAD_LD14__LD14 0xe0 + MX25_PAD_LD14__LD14 0xa0 MX25_PAD_LD15__LD15 0xe0 - MX25_PAD_GPIO_E__LD16 0xe0 - MX25_PAD_GPIO_F__LD17 0xe0 + MX25_PAD_GPIO_E__LD16 0xa0 + MX25_PAD_GPIO_F__LD17 0xa0 MX25_PAD_HSYNC__HSYNC 0xe0 MX25_PAD_VSYNC__VSYNC 0xe0 MX25_PAD_LSCLK__LSCLK 0xe0 @@ -244,7 +244,7 @@ MX25_PAD_UART1_RTS__UART1_RTS 0xe0 MX25_PAD_UART1_CTS__UART1_CTS 0xe0 MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + MX25_PAD_UART1_RXD__UART1_RXD 0x80 >; }; };