From patchwork Wed Jul 6 08:05:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 9215667 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 55863607D9 for ; Wed, 6 Jul 2016 08:08:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4778328771 for ; Wed, 6 Jul 2016 08:08:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3B8E628776; Wed, 6 Jul 2016 08:08:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AD15128771 for ; Wed, 6 Jul 2016 08:08:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bKhr9-0004OE-UM; Wed, 06 Jul 2016 08:06:51 +0000 Received: from mail-pf0-f195.google.com ([209.85.192.195]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bKhqv-0004I3-Fg; Wed, 06 Jul 2016 08:06:38 +0000 Received: by mail-pf0-f195.google.com with SMTP id i123so21191860pfg.3; Wed, 06 Jul 2016 01:06:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AjX0Uzophw1o3JHRQg0frLS0xZKmjfdYufsdcqrRcP8=; b=TYnAlCUjr6WuLqP/sWDxn5M3l7K89Rpo2A/XiW7edeq+FEDBEDixVJXrbUrKMwpFcw T1Pq1ZD5WZcrruoTOptflLRZLZ/nAfB3Aar6X6FiXJgCrQ4Q/K+tEMxdEBceBy0RA9FQ 8liHDfyo73YIqAZ+GLFEe9XCz19EmotUPAjNdiBalAtf4aENJJ8fnh5EHT2c4BW89wdS olhdv7nKbgFKehanhsDKM92eRkVZX89RiWRu3YZbzetoTxgrAgtEUa/r7LjPjsLXyvEp 3l8Ye7/FSzkUIPvwkgsiWgwdeX8Wx3slbM9Tdc81EA2ik9FPCGLwPDwiY/NMxUSSBlU9 qKEw== X-Gm-Message-State: ALyK8tJhIE0o8pszn5yCWVhufOdlvjHBBcu6zQ9BsbNir5qqhAOobGP9FrRqIwyixzx1Lg== X-Received: by 10.98.61.131 with SMTP id x3mr39716154pfj.115.1467792381546; Wed, 06 Jul 2016 01:06:21 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id cl15sm2492100pac.15.2016.07.06.01.06.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 06 Jul 2016 01:06:20 -0700 (PDT) From: Caesar Wang To: Marc Zyngier , Heiko Stuebner Subject: [PATCH v2 2/2] arm64: dts: rockchip: support the pmu node for rk3399 Date: Wed, 6 Jul 2016 16:05:57 +0800 Message-Id: <1467792357-9749-3-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467792357-9749-1-git-send-email-wxt@rock-chips.com> References: <1467792357-9749-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160706_010637_675242_6B070949 X-CRM114-Status: GOOD ( 10.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, huangtao@rock-chips.com, Xing Zheng , devicetree@vger.kernel.org, Catalin Marinas , Brian Norris , Will Deacon , dianders@chromium.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Rob Herring , David Wu , cf@rock-chips.com, Jianqun Xu , linux-arm-kernel@lists.infradead.org, Caesar Wang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add to enable the ARM Performance Monitor Units for rk3399. ARM cores often have a PMU for counting cpu and cache events like cache misses and hits. Also, as the Marc posted the patches [0] to support Partitioning per-cpu interrupts. Let's add this patch to match it on rk3399 SoCs. [0]: https://lkml.org/lkml/2016/4/11/182 https://patchwork.kernel.org/patch/9209369/ Signed-off-by: Caesar Wang Cc: Heiko Stuebner Cc: Marc Zyngier CC: linux-arm-kernel@lists.infradead.org --- Changes in v2: - AS Mark comments on https://patchwork.kernel.org/patch/9209369/ remove the interrupt-affinity property, we need depend on Marc' perf code on https://patchwork.kernel.org/patch/9209369/. arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 8f0a069..4bcd02b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -165,6 +165,16 @@ ; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + xin24m: xin24m { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -296,6 +306,16 @@ msi-controller; reg = <0x0 0xfee20000 0x0 0x20000>; }; + + ppi-partitions { + part0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + part1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; }; i2c1: i2c@ff110000 {