diff mbox

[v2,6/7] spi: s3c64xx: restore removed comments

Message ID 1467989201-14661-7-git-send-email-andi.shyti@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Andi Shyti July 8, 2016, 2:46 p.m. UTC
Patch a9e93e8 has erroneously removed some comments which are
important to understand why the bus frequency is multiplied by
two during the spi transfer.

Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
---
 drivers/spi/spi-s3c64xx.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Michael Turquette July 8, 2016, 4:17 p.m. UTC | #1
Quoting Andi Shyti (2016-07-08 07:46:40)
> Patch a9e93e8 has erroneously removed some comments which are
> important to understand why the bus frequency is multiplied by
> two during the spi transfer.
> 
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> ---
>  drivers/spi/spi-s3c64xx.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 6da663f..32b66f0 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -639,6 +639,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
>         writel(val, regs + S3C64XX_SPI_MODE_CFG);
>  
>         if (sdd->port_conf->clk_from_cmu) {
> +               /* There is half-multiplier before the SPI */
>                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);

Just a small comment, but if the fixed-factor divide-by-two clock was
modeled in Linux, then this driver could call clk_set_rate on that clock
with the "correct" rate.

I guess that this driver would be the provider of that clock?

Regards,
Mike

>         } else {
>                 /* Configure Clock */
> -- 
> 2.8.1
>
Andi Shyti July 8, 2016, 4:35 p.m. UTC | #2
Hi Mike,

> >         if (sdd->port_conf->clk_from_cmu) {
> > +               /* There is half-multiplier before the SPI */
> >                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
> 
> Just a small comment, but if the fixed-factor divide-by-two clock was
> modeled in Linux, then this driver could call clk_set_rate on that clock
> with the "correct" rate.
> 
> I guess that this driver would be the provider of that clock?

Makes sense, I will check it.

Thanks again,
Andi
Krzysztof Kozlowski July 8, 2016, 8:35 p.m. UTC | #3
On Fri, Jul 08, 2016 at 11:46:40PM +0900, Andi Shyti wrote:
> Patch a9e93e8 has erroneously removed some comments which are
> important to understand why the bus frequency is multiplied by
> two during the spi transfer.
> 
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> ---
>  drivers/spi/spi-s3c64xx.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 6da663f..32b66f0 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -639,6 +639,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
>  	writel(val, regs + S3C64XX_SPI_MODE_CFG);
>  
>  	if (sdd->port_conf->clk_from_cmu) {
> +		/* There is half-multiplier before the SPI */
>  		clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
>  	} else {
>  		/* Configure Clock */

Regardless of possible followup after Michael's comments:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof
On 07/08/2016 06:17 PM, Michael Turquette wrote:
> Quoting Andi Shyti (2016-07-08 07:46:40)

>> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
>> index 6da663f..32b66f0 100644
>> --- a/drivers/spi/spi-s3c64xx.c
>> +++ b/drivers/spi/spi-s3c64xx.c
>> @@ -639,6 +639,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
>>         writel(val, regs + S3C64XX_SPI_MODE_CFG);
>>  
>>         if (sdd->port_conf->clk_from_cmu) {
>> +               /* There is half-multiplier before the SPI */
>>                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
> 
> Just a small comment, but if the fixed-factor divide-by-two clock was
> modeled in Linux, then this driver could call clk_set_rate on that clock
> with the "correct" rate.
> 
> I guess that this driver would be the provider of that clock?

Good point, however I'm not sure if it is worth to model this divider
with a clk object.  It is an internal divider and the clock it provides
is only used internally within the SPI controller.  Thus the spi-s3c64xx
driver would be provider on the only consumer of this clock.

Additionally, the "There is half-multiplier before the SPI" comment
seems to be obfuscating how the hardware really looks like to me.
It talks about multiplier (which reminds me of PLLs with a divider
in the feedback loop) while there is a simple divider which should
be considered as an integral part of the controller IP block.

While we are at it, I'd propose to change this comment to something
like:

/* The SCLK_SPI clock is divided internally by 2 */
Michael Turquette July 11, 2016, 10:17 p.m. UTC | #5
Quoting Sylwester Nawrocki (2016-07-11 03:33:42)
> On 07/08/2016 06:17 PM, Michael Turquette wrote:
> > Quoting Andi Shyti (2016-07-08 07:46:40)
> 
> >> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> >> index 6da663f..32b66f0 100644
> >> --- a/drivers/spi/spi-s3c64xx.c
> >> +++ b/drivers/spi/spi-s3c64xx.c
> >> @@ -639,6 +639,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
> >>         writel(val, regs + S3C64XX_SPI_MODE_CFG);
> >>  
> >>         if (sdd->port_conf->clk_from_cmu) {
> >> +               /* There is half-multiplier before the SPI */
> >>                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
> > 
> > Just a small comment, but if the fixed-factor divide-by-two clock was
> > modeled in Linux, then this driver could call clk_set_rate on that clock
> > with the "correct" rate.
> > 
> > I guess that this driver would be the provider of that clock?
> 
> Good point, however I'm not sure if it is worth to model this divider
> with a clk object.  It is an internal divider and the clock it provides
> is only used internally within the SPI controller.  Thus the spi-s3c64xx
> driver would be provider on the only consumer of this clock.

Sure, but it's only a few lines of code to this, and there are examples
in the kernel already.

> 
> Additionally, the "There is half-multiplier before the SPI" comment
> seems to be obfuscating how the hardware really looks like to me.
> It talks about multiplier (which reminds me of PLLs with a divider
> in the feedback loop) while there is a simple divider which should
> be considered as an integral part of the controller IP block.
> 
> While we are at it, I'd propose to change this comment to something
> like:
> 
> /* The SCLK_SPI clock is divided internally by 2 */

It's your choice, but debug output would benefit from showing the real
clock frequency at some point.

Regards,
Mike
On 07/12/2016 12:17 AM, Michael Turquette wrote:
> Quoting Sylwester Nawrocki (2016-07-11 03:33:42)
>> On 07/08/2016 06:17 PM, Michael Turquette wrote:

> Sure, but it's only a few lines of code to this, and there are examples
> in the kernel already.
> 
>> Additionally, the "There is half-multiplier before the SPI" comment
>> seems to be obfuscating how the hardware really looks like to me.
>> It talks about multiplier (which reminds me of PLLs with a divider
>> in the feedback loop) while there is a simple divider which should
>> be considered as an integral part of the controller IP block.
>>
>> While we are at it, I'd propose to change this comment to something
>> like:
>>
>> /* The SCLK_SPI clock is divided internally by 2 */
> 
> It's your choice, but debug output would benefit from showing the real
> clock frequency at some point.

OK, it's indeed fairly easy to add a fixed rate divide-by-two clock,
but for the older SoCs we would need to also model the internal mux, gate,
and an 8-bit divider.  Then it becomes a bit bigger task. Anyway it might
be worth to try it, this could let us deprecate the samsung,spi-src-clk
property and for all the SoCs use assigned-clock-parents.
diff mbox

Patch

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 6da663f..32b66f0 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -639,6 +639,7 @@  static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 	writel(val, regs + S3C64XX_SPI_MODE_CFG);
 
 	if (sdd->port_conf->clk_from_cmu) {
+		/* There is half-multiplier before the SPI */
 		clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 	} else {
 		/* Configure Clock */