| Message ID | 1468932048-31635-4-git-send-email-juri.lelli@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Juri, On 19/07/16 13:40, Juri Lelli wrote: > Add TC2 cpu capacity binding information. > If you repost it, s/binding// > Cc: Liviu Dudau <liviu.dudau@arm.com> > Cc: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> (assuming you take it via some other tree, let us know if it's OK to merge the DTS separately and you want us to pick them)
Hi, On 10/08/16 16:33, Sudeep Holla wrote: > Hi Juri, > > On 19/07/16 13:40, Juri Lelli wrote: > >Add TC2 cpu capacity binding information. > > > > If you repost it, > > s/binding// > Yes, I think I'll need to repost, squashing the arm64 fix in the appropriate patch. Thanks. > >Cc: Liviu Dudau <liviu.dudau@arm.com> > >Cc: Sudeep Holla <sudeep.holla@arm.com> > > Acked-by: Sudeep Holla <sudeep.holla@arm.com> Thanks! > (assuming you take it via some other tree, let us know if it's > OK to merge the DTS separately and you want us to pick them) > As per off-line discussion with Russell, binding doc and arm bits should go via his patch system. While arm64 bits could go separately via aarch64. Does this make sense? Best, - Juri
On 10/08/16 16:43, Juri Lelli wrote: > Hi, > > On 10/08/16 16:33, Sudeep Holla wrote: >> Hi Juri, >> >> On 19/07/16 13:40, Juri Lelli wrote: >>> Add TC2 cpu capacity binding information. >>> >> >> If you repost it, >> >> s/binding// >> > > Yes, I think I'll need to repost, squashing the arm64 fix in the > appropriate patch. Thanks. > >>> Cc: Liviu Dudau <liviu.dudau@arm.com> >>> Cc: Sudeep Holla <sudeep.holla@arm.com> >> >> Acked-by: Sudeep Holla <sudeep.holla@arm.com> > > Thanks! > >> (assuming you take it via some other tree, let us know if it's >> OK to merge the DTS separately and you want us to pick them) >> > > As per off-line discussion with Russell, binding doc and arm bits should > go via his patch system. While arm64 bits could go separately via aarch64. > > Does this make sense? Yes, we can pick up the juno and tc2 dts changes and send it via arm-soc. I have already acked them, so you can take it via other tree if required.
On 10/08/16 16:52, Sudeep Holla wrote: > > > On 10/08/16 16:43, Juri Lelli wrote: > >Hi, > > > >On 10/08/16 16:33, Sudeep Holla wrote: > >>Hi Juri, > >> > >>On 19/07/16 13:40, Juri Lelli wrote: > >>>Add TC2 cpu capacity binding information. > >>> > >> > >>If you repost it, > >> > >>s/binding// > >> > > > >Yes, I think I'll need to repost, squashing the arm64 fix in the > >appropriate patch. Thanks. > > > >>>Cc: Liviu Dudau <liviu.dudau@arm.com> > >>>Cc: Sudeep Holla <sudeep.holla@arm.com> > >> > >>Acked-by: Sudeep Holla <sudeep.holla@arm.com> > > > >Thanks! > > > >>(assuming you take it via some other tree, let us know if it's > >> OK to merge the DTS separately and you want us to pick them) > >> > > > >As per off-line discussion with Russell, binding doc and arm bits should > >go via his patch system. While arm64 bits could go separately via aarch64. > > > >Does this make sense? > > Yes, we can pick up the juno and tc2 dts changes and send it via > arm-soc. If this works better for you it is fine by me! I'll only use Russell's system for docs and arm parsing/sysfs implementation then. Thanks, - Juri
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 0205c97efdef..45d08cc37b01 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -39,6 +39,7 @@ reg = <0>; cci-control-port = <&cci_control1>; cpu-idle-states = <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz = <1024>; }; cpu1: cpu@1 { @@ -47,6 +48,7 @@ reg = <1>; cci-control-port = <&cci_control1>; cpu-idle-states = <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -55,6 +57,7 @@ reg = <0x100>; cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; }; cpu3: cpu@3 { @@ -63,6 +66,7 @@ reg = <0x101>; cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; }; cpu4: cpu@4 { @@ -71,6 +75,7 @@ reg = <0x102>; cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; }; idle-states {
Add TC2 cpu capacity binding information. Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli <juri.lelli@arm.com> --- Changes from v1: - capacity-scale removed Changes from v4: - binding changed to capacity-dmips-mhz --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 5 +++++ 1 file changed, 5 insertions(+)