From patchwork Wed Jul 20 05:58:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 9238945 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0150A602F0 for ; Wed, 20 Jul 2016 06:07:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E4CDE277D9 for ; Wed, 20 Jul 2016 06:07:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D9426279E0; Wed, 20 Jul 2016 06:07:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=2.0 tests=BAYES_00,DKIM_ADSP_ALL, DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, UPPERCASE_50_75 autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B49A9277D9 for ; Wed, 20 Jul 2016 06:07:07 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bPkdE-0003lh-W2; Wed, 20 Jul 2016 06:05:21 +0000 Received: from new1-smtp.messagingengine.com ([66.111.4.221]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bPkYB-0005mA-DC for linux-arm-kernel@lists.infradead.org; Wed, 20 Jul 2016 06:00:12 +0000 Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailnew.nyi.internal (Postfix) with ESMTP id 02B25F44; Wed, 20 Jul 2016 01:59:50 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute2.internal (MEProxy); Wed, 20 Jul 2016 01:59:51 -0400 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-sasl-enc:x-sasl-enc; s=mesmtp; bh=DBoQY6SKPvmLuP1taS+kxWTHsDI =; b=TsXwguAMvZNIz5rxW+SrdpX8gF7aABci+65JYvM8PtATXH/aihKbNRfB6RC BGIrrxTIinhokVbeJ4MdmUFtDFcu4ugDsbM5yR4Grkwb+r+YDK19t1RlD5xIO6XR ZQqwHJuY6dlwsL9O16XQowiGa72/ZqvSWNdHddk61aJnwDOM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-sasl-enc:x-sasl-enc; s=smtpout; bh=DBoQ Y6SKPvmLuP1taS+kxWTHsDI=; b=bVmhzQqtqjMaG5YMuYk+gxdIZVgegZt1fHqS ZbcWb7wFz3PVutyEEcUXej434D5tA/kvgtidV7w3J18G1eOP5L0Zv+PJo13MnC6n hAo0KrQ1BEalnrZNAbrqBhXkual5FQzXH+fvrrn2/3r3Ru0vGYZiQ2U9O0XHLQEw cub89i4= X-Sasl-enc: lCIl+3IYjED7RMcXeIyxQDE8H2SFWn8QVuSyKCwKMR9P 1468994388 Received: from keelia.au.ibm.com (unknown [203.0.153.9]) by mail.messagingengine.com (Postfix) with ESMTPA id BE098CCDC0; Wed, 20 Jul 2016 01:59:44 -0400 (EDT) From: Andrew Jeffery To: Linus Walleij Subject: [PATCH 04/12] pinctrl: Add pinctrl-aspeed-g5 driver Date: Wed, 20 Jul 2016 15:28:25 +0930 Message-Id: <1468994313-13538-5-git-send-email-andrew@aj.id.au> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1468994313-13538-1-git-send-email-andrew@aj.id.au> References: <1468994313-13538-1-git-send-email-andrew@aj.id.au> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160719_230007_729820_9D8720C5 X-CRM114-Status: GOOD ( 14.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Alexandre Courbot , devicetree@vger.kernel.org, Andrew Jeffery , Benjamin Herrenschmidt , Russell King , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Rob Herring , Joel Stanley , linux-arm-kernel@lists.infradead.org, Jeremy Kerr MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docs Signed-off-by: Andrew Jeffery --- arch/arm/mach-aspeed/Kconfig | 1 + drivers/pinctrl/aspeed/Kconfig | 8 + drivers/pinctrl/aspeed/Makefile | 1 + drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 561 +++++++++++++++++++++++++++++ 4 files changed, 571 insertions(+) create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index 2589b90b0a7b..25a0ae01429e 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -25,6 +25,7 @@ config MACH_ASPEED_G5 bool "Aspeed SoC 5th Generation" depends on ARCH_MULTI_V6 select CPU_V6 + select PINCTRL_ASPEED_G5 help Say yes if you intend to run on an Aspeed ast2500 or similar fifth generation Aspeed BMCs. diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig index 480a206c69f1..ee45a965bc68 100644 --- a/drivers/pinctrl/aspeed/Kconfig +++ b/drivers/pinctrl/aspeed/Kconfig @@ -14,3 +14,11 @@ config PINCTRL_ASPEED_G4 help Say Y here to enable pin controller support for Aspeed's 4th generation AST SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G5 + bool "Aspeed G5 SoC pin control" + depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 5th + generation AST SoCs. GPIO is provided by a separate GPIO driver. diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile index 253bddd1fc2d..0f4b8760f936 100644 --- a/drivers/pinctrl/aspeed/Makefile +++ b/drivers/pinctrl/aspeed/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o +obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c new file mode 100644 index 000000000000..737a33b05ea2 --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -0,0 +1,561 @@ +/* + * Copyright (C) 2016 IBM Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-aspeed.h" + +#define ASPEED_G5_NR_PINS 228 + +#define COND1 SIG_DESC_BIT(SCU90, 6, 0) +#define COND2 { SCU94, GENMASK(1, 0), 0, 0 } + +#define I2C9_DESC SIG_DESC_SET(SCU90, 22) + +#define C14 4 +SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1); +MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5); + +FUNC_GROUP_DECL(TIMER5, C14); + +#define A13 5 +SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1); +MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6); + +FUNC_GROUP_DECL(TIMER6, A13); + +FUNC_GROUP_DECL(I2C9, C14, A13); + +#define SD1_DESC SIG_DESC_SET(SCU90, 0) + +#define C12 16 +#define I2C10_DESC SIG_DESC_SET(SCU90, 23) +SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); +MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10); + +#define A12 17 +SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); +MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10); + +FUNC_GROUP_DECL(I2C10, C12, A12); + +#define B12 18 +#define I2C11_DESC SIG_DESC_SET(SCU90, 24) +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); +MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11); + +#define D9 19 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); +MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11); + +FUNC_GROUP_DECL(I2C11, B12, D9); + +#define D10 20 +#define I2C12_DESC SIG_DESC_SET(SCU90, 25) +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); +MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12); + +#define E12 21 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); +MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12); + +FUNC_GROUP_DECL(I2C12, D10, E12); + +#define C11 22 +#define I2C13_DESC SIG_DESC_SET(SCU90, 26) +SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); +MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13); + +#define B11 23 +SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); +MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13); + +FUNC_GROUP_DECL(I2C13, C11, B11); +FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11); + +#define SD2_DESC SIG_DESC_SET(SCU90, 1) +#define GPID0_DESC SIG_DESC_SET(SCU8C, 8) +#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) + +#define F19 24 +SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); +SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); +MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN); + +#define E21 25 +SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); +SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); +MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT); + +FUNC_GROUP_DECL(GPID0, F19, E21); + +#define GPID1_DESC SIG_DESC_SET(SCU8C, 9) + +#define D20 26 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID1IN, GPID1, GPID1_DESC); +SIG_EXPR_DECL(GPID1IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID1IN, GPID1, GPID); +MS_PIN_DECL(D20, GPIOD2, SD2DAT0, GPID1IN); + +#define D21 27 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID1OUT, GPID1, GPID1_DESC); +SIG_EXPR_DECL(GPID1OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID1OUT, GPID1, GPID); +MS_PIN_DECL(D21, GPIOD3, SD2DAT1, GPID1OUT); + +FUNC_GROUP_DECL(GPID1, D20, D21); + +#define I2C5_DESC SIG_DESC_SET(SCU90, 18) + +#define L3 80 +SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); +SS_PIN_DECL(L3, GPIOK0, SCL5); + +#define L4 81 +SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); +SS_PIN_DECL(L4, GPIOK1, SDA5); + +FUNC_GROUP_DECL(I2C5, L3, L4); + +#define I2C6_DESC SIG_DESC_SET(SCU90, 19) + +#define L1 82 +SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); +SS_PIN_DECL(L1, GPIOK2, SCL6); + +#define N2 83 +SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); +SS_PIN_DECL(N2, GPIOK3, SDA6); + +FUNC_GROUP_DECL(I2C6, L1, N2); + +#define I2C7_DESC SIG_DESC_SET(SCU90, 20) + +#define N1 84 +SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); +SS_PIN_DECL(N1, GPIOK4, SCL7); + +#define P1 85 +SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); +SS_PIN_DECL(P1, GPIOK5, SDA7); + +FUNC_GROUP_DECL(I2C7, N1, P1); + +#define I2C8_DESC SIG_DESC_SET(SCU90, 21) + +#define P2 86 +SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); +SS_PIN_DECL(P2, GPIOK6, SCL8); + +#define R1 87 +SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); +SS_PIN_DECL(R1, GPIOK7, SDA8); + +FUNC_GROUP_DECL(I2C8, P2, R1); + +#define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 } +#define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 } +#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 } +#define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 } + +#define V2 104 +#define V2_DESC SIG_DESC_SET(SCU88, 0) +SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2); +MS_PIN_DECL(V2, GPION0, DASHN0, PWM0); +FUNC_GROUP_DECL(PWM0, V2); + +#define W2 105 +#define W2_DESC SIG_DESC_SET(SCU88, 1) +SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2); +MS_PIN_DECL(W2, GPION1, DASHN1, PWM1); +FUNC_GROUP_DECL(PWM1, W2); + +#define V3 106 +#define V3_DESC SIG_DESC_SET(SCU88, 2) +SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2); +SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2); +MS_PIN_DECL(V3, GPION2, VPIG2, PWM2); +FUNC_GROUP_DECL(PWM2, V3); + +#define U3 107 +#define U3_DESC SIG_DESC_SET(SCU88, 3) +SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2); +SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2); +MS_PIN_DECL(U3, GPION3, VPIG3, PWM3); +FUNC_GROUP_DECL(PWM3, U3); + +#define W3 108 +#define W3_DESC SIG_DESC_SET(SCU88, 4) +SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2); +SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2); +MS_PIN_DECL(W3, GPION4, VPIG4, PWM4); +FUNC_GROUP_DECL(PWM4, W3); + +#define AA3 109 +#define AA3_DESC SIG_DESC_SET(SCU88, 5) +SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2); +SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2); +MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5); +FUNC_GROUP_DECL(PWM5, AA3); + +#define Y3 110 +#define Y3_DESC SIG_DESC_SET(SCU88, 6) +SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2); +MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6); +FUNC_GROUP_DECL(PWM6, Y3); + +#define T4 111 +#define T4_DESC SIG_DESC_SET(SCU88, 7) +SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2); +MS_PIN_DECL(T4, GPION7, VPIG7, PWM7); +FUNC_GROUP_DECL(PWM7, T4); + +#define I2C3_DESC SIG_DESC_SET(SCU90, 16) + +#define A11 128 +SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); +SS_PIN_DECL(A11, GPIOQ0, SCL3); + +#define A10 129 +SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); +SS_PIN_DECL(A10, GPIOQ1, SDA3); + +FUNC_GROUP_DECL(I2C3, A11, A10); + +#define I2C4_DESC SIG_DESC_SET(SCU90, 17) + +#define A9 130 +SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); +SS_PIN_DECL(A9, GPIOQ2, SCL4); + +#define B9 131 +SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); +SS_PIN_DECL(B9, GPIOQ3, SDA4); + +FUNC_GROUP_DECL(I2C4, A9, B9); + +#define I2C14_DESC SIG_DESC_SET(SCU90, 27) + +#define N21 132 +SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); +SS_PIN_DECL(N21, GPIOQ4, SCL14); + +#define N22 133 +SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); +SS_PIN_DECL(N22, GPIOQ5, SDA14); + +FUNC_GROUP_DECL(I2C14, N21, N22); + +/* RGMII1/RMII1 */ + +#define MAC1_RMII { HW_STRAP1, BIT(6), 0, 0 } + +#define B5 152 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, MAC1_RMII, + SIG_DESC_SET(SCU48, 29)); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1); +MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO), + SIG_EXPR_LIST_PTR(RGMII1TXCK)); + +#define E9 153 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1); +MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN), + SIG_EXPR_LIST_PTR(RGMII1TXCTL)); + +#define F9 154 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1); +MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0), + SIG_EXPR_LIST_PTR(RGMII1TXD0)); + +#define A5 155 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1); +MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1), + SIG_EXPR_LIST_PTR(RGMII1TXD1)); + +#define E7 156 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1); +MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0), + SIG_EXPR_LIST_PTR(RGMII1TXD2)); + +#define D7 157 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); +MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1), + SIG_EXPR_LIST_PTR(RGMII1TXD3)); + +#define B4 164 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1); +MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI), + SIG_EXPR_LIST_PTR(RGMII1RXCK)); + +#define A4 165 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1); +MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2), + SIG_EXPR_LIST_PTR(RGMII1RXCTL)); + +#define A3 166 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1); +MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0), + SIG_EXPR_LIST_PTR(RGMII1RXD0)); + +#define D6 167 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1); +MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1), + SIG_EXPR_LIST_PTR(RGMII1RXD1)); + +#define C5 168 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1); +MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV), + SIG_EXPR_LIST_PTR(RGMII1RXD2)); + +#define C4 169 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); +SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, MAC1_RMII); +SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); +MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), + SIG_EXPR_LIST_PTR(RGMII1RXD3)); + +FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7); +FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5); + +static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { + ASPEED_PINCTRL_PIN(C14), + ASPEED_PINCTRL_PIN(A13), + ASPEED_PINCTRL_PIN(C12), + ASPEED_PINCTRL_PIN(A12), + ASPEED_PINCTRL_PIN(B12), + ASPEED_PINCTRL_PIN(D9), + ASPEED_PINCTRL_PIN(D10), + ASPEED_PINCTRL_PIN(E12), + ASPEED_PINCTRL_PIN(C11), + ASPEED_PINCTRL_PIN(B11), + ASPEED_PINCTRL_PIN(F19), + ASPEED_PINCTRL_PIN(E21), + ASPEED_PINCTRL_PIN(D20), + ASPEED_PINCTRL_PIN(D21), + ASPEED_PINCTRL_PIN(L3), + ASPEED_PINCTRL_PIN(L4), + ASPEED_PINCTRL_PIN(L1), + ASPEED_PINCTRL_PIN(N2), + ASPEED_PINCTRL_PIN(N1), + ASPEED_PINCTRL_PIN(P1), + ASPEED_PINCTRL_PIN(P2), + ASPEED_PINCTRL_PIN(R1), + ASPEED_PINCTRL_PIN(V2), + ASPEED_PINCTRL_PIN(W2), + ASPEED_PINCTRL_PIN(V3), + ASPEED_PINCTRL_PIN(U3), + ASPEED_PINCTRL_PIN(W3), + ASPEED_PINCTRL_PIN(AA3), + ASPEED_PINCTRL_PIN(Y3), + ASPEED_PINCTRL_PIN(T4), + ASPEED_PINCTRL_PIN(A11), + ASPEED_PINCTRL_PIN(A10), + ASPEED_PINCTRL_PIN(A9), + ASPEED_PINCTRL_PIN(B9), + ASPEED_PINCTRL_PIN(N21), + ASPEED_PINCTRL_PIN(N22), + ASPEED_PINCTRL_PIN(D10), + ASPEED_PINCTRL_PIN(E12), + ASPEED_PINCTRL_PIN(B4), + ASPEED_PINCTRL_PIN(A4), + ASPEED_PINCTRL_PIN(A3), + ASPEED_PINCTRL_PIN(D6), + ASPEED_PINCTRL_PIN(C5), + ASPEED_PINCTRL_PIN(C4), + ASPEED_PINCTRL_PIN(B5), + ASPEED_PINCTRL_PIN(E9), + ASPEED_PINCTRL_PIN(F9), + ASPEED_PINCTRL_PIN(A5), + ASPEED_PINCTRL_PIN(E7), + ASPEED_PINCTRL_PIN(D7), +}; + +static const struct aspeed_pin_group aspeed_g5_groups[] = { + ASPEED_PINCTRL_GROUP(I2C9), + ASPEED_PINCTRL_GROUP(I2C10), + ASPEED_PINCTRL_GROUP(I2C11), + ASPEED_PINCTRL_GROUP(I2C12), + ASPEED_PINCTRL_GROUP(I2C13), + ASPEED_PINCTRL_GROUP(SD1), + ASPEED_PINCTRL_GROUP(GPID0), + ASPEED_PINCTRL_GROUP(GPID1), + ASPEED_PINCTRL_GROUP(I2C5), + ASPEED_PINCTRL_GROUP(I2C6), + ASPEED_PINCTRL_GROUP(I2C7), + ASPEED_PINCTRL_GROUP(I2C8), + ASPEED_PINCTRL_GROUP(PWM0), + ASPEED_PINCTRL_GROUP(PWM1), + ASPEED_PINCTRL_GROUP(PWM2), + ASPEED_PINCTRL_GROUP(PWM3), + ASPEED_PINCTRL_GROUP(PWM4), + ASPEED_PINCTRL_GROUP(PWM5), + ASPEED_PINCTRL_GROUP(PWM6), + ASPEED_PINCTRL_GROUP(PWM7), + ASPEED_PINCTRL_GROUP(I2C3), + ASPEED_PINCTRL_GROUP(I2C4), + ASPEED_PINCTRL_GROUP(I2C14), + ASPEED_PINCTRL_GROUP(RMII1), + ASPEED_PINCTRL_GROUP(RGMII1), +}; + +static const struct aspeed_pin_function aspeed_g5_functions[] = { + ASPEED_PINCTRL_FUNC(I2C9), + ASPEED_PINCTRL_FUNC(I2C10), + ASPEED_PINCTRL_FUNC(I2C11), + ASPEED_PINCTRL_FUNC(I2C12), + ASPEED_PINCTRL_FUNC(I2C13), + ASPEED_PINCTRL_FUNC(SD1), + ASPEED_PINCTRL_FUNC(GPID0), + ASPEED_PINCTRL_FUNC(GPID1), + ASPEED_PINCTRL_FUNC(I2C5), + ASPEED_PINCTRL_FUNC(I2C6), + ASPEED_PINCTRL_FUNC(I2C7), + ASPEED_PINCTRL_FUNC(I2C8), + ASPEED_PINCTRL_FUNC(PWM0), + ASPEED_PINCTRL_FUNC(PWM1), + ASPEED_PINCTRL_FUNC(PWM2), + ASPEED_PINCTRL_FUNC(PWM3), + ASPEED_PINCTRL_FUNC(PWM4), + ASPEED_PINCTRL_FUNC(PWM5), + ASPEED_PINCTRL_FUNC(PWM6), + ASPEED_PINCTRL_FUNC(PWM7), + ASPEED_PINCTRL_FUNC(I2C3), + ASPEED_PINCTRL_FUNC(I2C4), + ASPEED_PINCTRL_FUNC(I2C14), + ASPEED_PINCTRL_FUNC(RMII1), + ASPEED_PINCTRL_FUNC(RGMII1), +}; + +static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { + .pins = aspeed_g5_pins, + .npins = ARRAY_SIZE(aspeed_g5_pins), + .groups = aspeed_g5_groups, + .ngroups = ARRAY_SIZE(aspeed_g5_groups), + .functions = aspeed_g5_functions, + .nfunctions = ARRAY_SIZE(aspeed_g5_functions), +}; + +static struct pinmux_ops aspeed_g5_pinmux_ops = { + .get_functions_count = aspeed_pinmux_get_fn_count, + .get_function_name = aspeed_pinmux_get_fn_name, + .get_function_groups = aspeed_pinmux_get_fn_groups, + .set_mux = aspeed_pinmux_set_mux, + .gpio_request_enable = aspeed_gpio_request_enable, + .strict = true, +}; + +static struct pinctrl_ops aspeed_g5_pinctrl_ops = { + .get_groups_count = aspeed_pinctrl_get_groups_count, + .get_group_name = aspeed_pinctrl_get_group_name, + .get_group_pins = aspeed_pinctrl_get_group_pins, + .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_free_map, +}; + +static struct pinctrl_desc aspeed_g5_pinctrl_desc = { + .name = "aspeed-g5-pinctrl", + .pins = aspeed_g5_pins, + .npins = ARRAY_SIZE(aspeed_g5_pins), + .pctlops = &aspeed_g5_pinctrl_ops, + .pmxops = &aspeed_g5_pinmux_ops, +}; + +static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++) + aspeed_g5_pins[i].number = i; + + return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc, + &aspeed_g5_pinctrl_data); +} + +static const struct of_device_id aspeed_g5_pinctrl_of_match[] = { + { .compatible = "aspeed,g5-pinctrl", }, + { }, +}; + +static struct platform_driver aspeed_g5_pinctrl_driver = { + .probe = aspeed_g5_pinctrl_probe, + .driver = { + .name = "aspeed-g5-pinctrl", + .of_match_table = aspeed_g5_pinctrl_of_match, + }, +}; + +static int aspeed_g5_pinctrl_init(void) +{ + return platform_driver_register(&aspeed_g5_pinctrl_driver); +} + +arch_initcall(aspeed_g5_pinctrl_init);