From patchwork Fri Jul 22 08:48:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tan Xiaojun X-Patchwork-Id: 9243179 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F3DC460757 for ; Fri, 22 Jul 2016 08:42:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E32C226246 for ; Fri, 22 Jul 2016 08:42:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D5DE327F9A; Fri, 22 Jul 2016 08:42:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7C6C426246 for ; Fri, 22 Jul 2016 08:42:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bQW0p-0002pK-3h; Fri, 22 Jul 2016 08:40:51 +0000 Received: from szxga03-in.huawei.com ([119.145.14.66]) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bQW0O-0001G6-I1 for linux-arm-kernel@lists.infradead.org; Fri, 22 Jul 2016 08:40:30 +0000 Received: from 172.24.1.36 (EHLO szxeml425-hub.china.huawei.com) ([172.24.1.36]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id CFE39756; Fri, 22 Jul 2016 16:38:09 +0800 (CST) Received: from localhost.localdomain (10.175.102.38) by szxeml425-hub.china.huawei.com (10.82.67.180) with Microsoft SMTP Server id 14.3.235.1; Fri, 22 Jul 2016 16:37:58 +0800 From: Tan Xiaojun To: , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH v1 1/2] Documentation: arm64: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts bindings Date: Fri, 22 Jul 2016 16:48:51 +0800 Message-ID: <1469177332-72156-2-git-send-email-tanxiaojun@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1469177332-72156-1-git-send-email-tanxiaojun@huawei.com> References: <1469177332-72156-1-git-send-email-tanxiaojun@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.102.38] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5791DB72.003F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 34496272d13ef2d19e7d6e5299b6d65c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160722_014025_261414_CB0C8FCC X-CRM114-Status: UNSURE ( 7.64 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP First, add Hisilicon HiP05/06/07 CPU and ALGSUB system controller dts bindings. Then, add Hisilicon Djtag dts binding. Signed-off-by: Tan Xiaojun --- .../bindings/arm/hisilicon/hisilicon.txt | 98 ++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 83fe816..82a22ed 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -249,3 +249,101 @@ Required Properties: [1]: bootwrapper size [2]: relocation physical address [3]: relocation size + +----------------------------------------------------------------------- +Hisilicon HiP05 CPU system controller +Required properties: +- compatible : "hisilicon,hip05-sysctrl", "syscon", "simple-mfd"; +- reg : Register address and size +- djtag : + - compatible : "hisilicon,hip05-cpu-djtag-v1" + - syscon : which sysctrl node + +Hisilicon HiP06 CPU system controller +Required properties: +- compatible : "hisilicon,hip06-sysctrl", "syscon", "simple-mfd"; +- reg : Register address and size +- djtag : + - compatible : "hisilicon,hip06-cpu-djtag-v1" + - syscon : which sysctrl node + +Hisilicon HiP07 CPU system controller +Required properties: +- compatible : "hisilicon,hip07-sysctrl", "syscon", "simple-mfd"; +- reg : Register address and size +- djtag : + - compatible : "hisilicon,hip07-cpu-djtag-v2" + - syscon : which sysctrl node + +The Hisilicon HiP05/06/07 CPU system controller is in CPU die of SoC. It is +used to control system operation mode, control system operating status and +manage some important modules (such as clock, reset, soft reset, secure +debugger, etc.). We can also configure some functions of the peripheral +devices and query their status by it. + +The Hisilicon Djtag in CPU die is an independent module which connects with +some modules in the SoC by Debug Bus. This module can be configured to access +the registers of connecting modules (like L3 cache) during real time debugging +by sysctrl. + +Example: + /* for Hisilicon HiP05 sysctrl */ + hip05-sysctrl: hip05-sysctrl@80010000 { + compatible = "hisilicon,hip05-sysctrl", "syscon", "simple-mfd"; + reg = <0x80010000 0x10000>; + + djtag0: djtag@0 { + compatible = "hisilicon,hip05-cpu-djtag-v1"; + syscon = <&hip05-sysctrl>; + }; + }; + + /* for Hisilicon HiP05 l3 cache maybe set like below */ + llc0: llc@0 { + compatible = "hisilicon,hip05-llc"; + djtag = <&djtag0>; + }; + +----------------------------------------------------------------------- +Hisilicon HiP05 ALGSUB system controller +Required properties: +- compatible : "hisilicon,hip05-alg-sysctrl", "syscon", "simple-mfd"; +- reg : Register address and size +- djtag : + - compatible : "hisilicon,hip05-io-djtag-v1" + - syscon : which sysctrl node + +Hisilicon HiP06 ALGSUB system controller +Required properties: +- compatible : "hisilicon,hip06-alg-sysctrl", "syscon", "simple-mfd"; +- reg : Register address and size +- djtag : + - compatible : "hisilicon,hip06-io-djtag-v2" + - syscon : which sysctrl node + +Hisilicon HiP07 ALGSUB system controller +Required properties: +- compatible : "hisilicon,hip07-alg-sysctrl", "syscon", "simple-mfd"; +- reg : Register address and size +- djtag : + - compatible : "hisilicon,hip07-io-djtag-v2" + - syscon : which sysctrl node + +The Hisilicon HiP05/06/07 ALGSUB system controller is in IO die of SoC. It +has a similar function as the Hisilicon HiP05/06/07 CPU system controller +in CPU die and it manage default modules, like RSA, etc. + +The Hisilicon Djtag in IO die has a similar function as the one in CPU die. + +Example: + /* for Hisilicon HiP05 alg subctrl */ + hip05-alg-sysctrl: hip05-alg-sysctrl@d0000000 { + compatible = "hisilicon,hip05-alg-sysctrl", "syscon", "simple-mfd"; + reg = <0xd0000000 0x10000>; + + djtag0: djtag@0 { + compatible = "hisilicon,hip05-io-djtag-v1"; + syscon = <&hip05-alg-sysctrl>; + }; + }; +