From patchwork Wed Aug 3 06:34:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anurup M X-Patchwork-Id: 9260821 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 38F4760754 for ; Wed, 3 Aug 2016 06:38:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B624284FB for ; Wed, 3 Aug 2016 06:38:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 201B22854D; Wed, 3 Aug 2016 06:38:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B245E284FB for ; Wed, 3 Aug 2016 06:38:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bUpnU-0006Ku-G2; Wed, 03 Aug 2016 06:36:56 +0000 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bUpnB-0006BD-Pd for linux-arm-kernel@lists.infradead.org; Wed, 03 Aug 2016 06:36:39 +0000 Received: by mail-pf0-x243.google.com with SMTP id h186so13971719pfg.2 for ; Tue, 02 Aug 2016 23:36:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mhhxXmhP+dG/CXzxmIt7H8iieCUWORMelDY+icX3f8A=; b=ymKtZTDgSwJG5LHTBfJo0ia9QYaLDDlvfkySHq8Jsi0DxmF/8o58+ZZUXmxQ/F81tY ozf2tVQmcDiq64i/bYWPuiCOgeE095ECaT9BZuJJtjOOcua5lW12k9PXtqGWi3xOrnaX fDyOk0ypZVnqsKZldAuSJqj69VxiZL32Uqg0UARo7NzbvFjG8M0DuFFC4m/oXxiErAW3 bjgfpRppTbEgMiD5KbrQPXIHChjQ8G9YDiPKwqX6pkWnP4c0+LIcVWzqR6IcdOo2a7WJ BeTF29HUUc6bvC//nLX3wbcM3ro5VoFRDn6khYIJbXaxUnzwshqkfa06iPXOZUepZwed 6dVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mhhxXmhP+dG/CXzxmIt7H8iieCUWORMelDY+icX3f8A=; b=YwSIvhcCd7FX0ig4lw/PLZ+7nm3rwT/Y0JIZIbd/1nd40zW71dw9dRwGhHvbMHhdEe fI2Fj0E5iVKKcYMEVkHFTkFU7Qs2/ztM/n5/P1WceFB2y3vuzguPsnqsKqe+AjrMpl1a XGQ15jieOftJ8RvV1hOoY+R7NJfhRq+3HGeiW89DzQF129Oct9pKfnUJmB2yqwSA5uVu 8erbrjO+NooImWyceJg+3TnTKQQHnvflbmzdKNIynh1EgnLOYo3DQAHr8DE71P9tKlL7 +h5SZLekBFdT9z61iU6Lcr8q5cvCN1pMUwvcdGC8kBt68T27MWi/zH9E/7UDaaMrNMsT wzGQ== X-Gm-Message-State: AEkoous2zVonJviI9u3pjUC71cSKTY7tj3xgB5mbtr1Xf2FMV7iaZ5l6a2zDke2Kq+MfXg== X-Received: by 10.98.200.29 with SMTP id z29mr111840043pff.143.1470206181779; Tue, 02 Aug 2016 23:36:21 -0700 (PDT) Received: from localhost.localdomain ([14.141.5.98]) by smtp.gmail.com with ESMTPSA id vt10sm9347585pab.43.2016.08.02.23.36.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 02 Aug 2016 23:36:21 -0700 (PDT) From: Anurup M X-Google-Original-From: Anurup M To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v1 03/10] arm64:perf: Add Documentaion for HIP05 PMU event counting. 1. Documentaion for perf usage and PMU events. Date: Wed, 3 Aug 2016 02:34:32 -0400 Message-Id: <1470206079-73280-4-git-send-email-anurup.m@huawei.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1470206079-73280-1-git-send-email-anurup.m@huawei.com> References: <1470206079-73280-1-git-send-email-anurup.m@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160802_233637_993176_00BE7B92 X-CRM114-Status: GOOD ( 14.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, z.liuxinliang@hisilicon.com, gabriele.paoloni@huawei.com, john.garry@huawei.com, will.deacon@arm.com, xuwei5@hisilicon.com, zhangshaokun@hisilicon.com, sanil.kumar@hisilicon.com, Anurup M , dingtianhong@huawei.com, anthony.iliopoulos@huawei.com, shyju.pv@huawei.com, tanxiaojun@huawei.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Anurup M Signed-off-by: Shaokun Zhang --- Documentation/perf/hip05-pmu.txt | 70 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/perf/hip05-pmu.txt diff --git a/Documentation/perf/hip05-pmu.txt b/Documentation/perf/hip05-pmu.txt new file mode 100644 index 0000000..fd9ca26 --- /dev/null +++ b/Documentation/perf/hip05-pmu.txt @@ -0,0 +1,70 @@ +Hisilicon Hip05 SoC PMU (Performance Monitoring Unit) +===================================================== +The Hisilicon Hip05 chip consists of varous independent system device PMU's +such as L3 cache (LLC) and Miscellaneous Nodes(MN). These PMU devices are +independent and have hardware logic to gather statistics and performance +information. + +Hip05 is encapsulated by multiple CPU and IO die's. The CPU die is called as +Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL is further +grouped as CPU clusters (CCL) which includes 4 cpu-cores each. +Each SCCL has 1 L3 cache and 1 MN units. + +The L3 cache (LLC) is shared by all CPU cores in a CPU die. The LLC has four +banks (or instances). Each bank or instance of LLC has Eight 32-bit counter +registers to count the 22 different statistics events. These events are very +useful for debugging. The LLC support overflow interrupt for its 8 counter +registers. + +The MN module is also shared by all CPU cores in a CPU die. It receives +barriers and DVM(Distributed Virtual Memory) messages from cpu or smmu, and +perform the required actions and return response messages. These events are +very useful for debugging. The MN has total 9 statistics events and support +four 32-bit counter registers. The MN support overflow interrupt for its 4 +counter registers. + +There is no memory mapping for L3 cache and MN. It can be accessed by using +the Hisilicon djtag interface. The Djtag in a SCCL is an independent module +which connects with some modules in the SoC by Debug Bus. + +HIP05 PMU driver +---------------- +The HIP05 PMU driver shall register perf PMU drivers for L3 cache and MN. +The available events and configuration options shall be described in the sysfs. +The "perf list" shall list the available events from sysfs. +eg. hip05_l3c/read_allocate,cpu_die=?,bank=?/ [kernel PMU event] + +The event code contains the information about the cpudie, module, banks and +the event code. +These are represented in Perf event attributes as + i) event 0-11 + The event code will be represented using the LSB 12 bits. + ii) bank 12-15 + The Banks or no of instances are with 4 bits. For PMU which + have only single instance, this field will be ignored. For L3 + Cache, this will identify the bank. The 0xf value shall sum the + count in all available banks. + iii) cpu_cluster 16-19 + This identfies the CPU cluster (CCL) which share this PMU. For + L3 Cache, MN, DDRC etc. which are shared for a SCCL, this field + will be ignored. For modules shared by a CPU cluster this can + represent the cluster ID. This filed is reserved and unused now. + iv) cpu_die 20-23 + This identfies the supper CPU cluster (SCCL) which share this + PMU. For L3 Cache, MN, DDRC etc. which are shared for a SCCL + this field represent the CPU die ID or (SCCL ID). + +Example usage of perf: +$# perf list +hisi_l3c/read_allocate,cpu_die=?,bank=?/ [kernel PMU event] +hisi_l3c/read_hit,cpu_die=?,bank=?/ [kernel PMU event] +hisi_l3c/write_hit,cpu_die=?,bank=?/ [kernel PMU event] +------------------------------------------------------- +------------------------------------------------------- + +$# perf stat -a -e hisi_l3c/read_allocate,cpu_die=0x2,bank=0xf/ sleep 5 + +$# perf stat -C 0 -A -e hisi_l3c/read_allocate,cpu_die=0x2,bank=0xf/ ls -l + +The current driver doesnot support sampling. so "perf record" is unsupported. +Also attach to a task is unsupported as the events are all uncore.