From patchwork Wed Aug 3 06:34:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anurup M X-Patchwork-Id: 9260825 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A9B2B60754 for ; Wed, 3 Aug 2016 06:39:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A50D284FB for ; Wed, 3 Aug 2016 06:39:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8BF142854D; Wed, 3 Aug 2016 06:39:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 46CF3284FB for ; Wed, 3 Aug 2016 06:39:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bUpoF-0006hW-LH; Wed, 03 Aug 2016 06:37:43 +0000 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bUpnL-0006CC-Qa for linux-arm-kernel@lists.infradead.org; Wed, 03 Aug 2016 06:36:49 +0000 Received: by mail-pf0-x241.google.com with SMTP id i6so14026609pfe.0 for ; Tue, 02 Aug 2016 23:36:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b7Fwc/lmbfTSkYRUgC3FzzLGXpLAkVT/+R0LSJ9XA7I=; b=Mw9oc7XOe3wfZVWgJ0tnqOMNdDeWZkVlPAO0s9lVs3EHZsx1jQPnPoG/AwGRnI+YAg bjs1aYOkLegeMcHj9vZ7DfwbNCvU5CwwALFiTplNFvbKbxO0z3I1ALWlLUrJNYLr6ae8 mtp9Hx77+niXfH+v+ZJYF0Zl+9xYWlNcKlHIzm2wLZzEXbza2qEqSGN6CNSMskRM+GMj M3fZjo0I38fv6jZI41AZ1eus/T5lBeNgNOLpDspfqdITHKAkgR8iueXq9ZJs5w/gXzj5 yPc7tX+us0Gnjcw9k/pckc/8JQHzOKsQcas2ofstAN274jtSuRurauIGmmtHfheLUlwI B1Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b7Fwc/lmbfTSkYRUgC3FzzLGXpLAkVT/+R0LSJ9XA7I=; b=Eiq/q3HL2XfGf4jg5BhChm5MmC/hge8qvOLChnakWgPCzS7dTDbPgezWLR/jOmT8dM psQJ9virGCLJiFwo5cMokMpHvdNaNYbwp6KfVSZXmvjK1OfjE6gFzZVwlGnYgSg0Pkx3 /FEZIAmhh8omBYpvZ2Ohfkqtjd8hMw5WWIjzzQexkr66PcgsgUvDOuJ5N0+4PDhGi3WR nJVfgkuTuOXTZwdM45Sx4Ogn4leuQ8CBVxzGT38APUWxOK4PeVNcuYw33meJN/j3mf2v GQGkHRWcp/vAS10lPDfE5oFbm0nv9RQjzhZ1pTO7xyjp7ILxh53ta688erSQYWqn13oR cIZA== X-Gm-Message-State: AEkoouu2IqwvYwWDrz0iILSurSPAgy2gsZ8+mF7k/DeKhAxrHotOWs31aTzUu8gK0+gwCw== X-Received: by 10.98.13.84 with SMTP id v81mr114101072pfi.108.1470206186964; Tue, 02 Aug 2016 23:36:26 -0700 (PDT) Received: from localhost.localdomain ([14.141.5.98]) by smtp.gmail.com with ESMTPSA id vt10sm9347585pab.43.2016.08.02.23.36.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 02 Aug 2016 23:36:26 -0700 (PDT) From: Anurup M X-Google-Original-From: Anurup M To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v1 04/10] arm64:perf: Add Devicetree bindings for Hisilicon SoC PMU Date: Wed, 3 Aug 2016 02:34:33 -0400 Message-Id: <1470206079-73280-5-git-send-email-anurup.m@huawei.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1470206079-73280-1-git-send-email-anurup.m@huawei.com> References: <1470206079-73280-1-git-send-email-anurup.m@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160802_233647_962179_A706F3E8 X-CRM114-Status: GOOD ( 14.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, z.liuxinliang@hisilicon.com, gabriele.paoloni@huawei.com, john.garry@huawei.com, will.deacon@arm.com, xuwei5@hisilicon.com, zhangshaokun@hisilicon.com, sanil.kumar@hisilicon.com, Anurup M , dingtianhong@huawei.com, anthony.iliopoulos@huawei.com, shyju.pv@huawei.com, tanxiaojun@huawei.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP 1) Device tree bindings for Hisilicon Hip05 PMU. 2) Add example for Hisilicon L3 cache and MN PMU. Signed-off-by: Anurup M Signed-off-by: Shaokun Zhang --- .../devicetree/bindings/arm/hisilicon/pmu.txt | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt new file mode 100644 index 0000000..ba540db --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt @@ -0,0 +1,52 @@ +Hisilicon SoC HIP05 ARMv8 PMU + +The Hisilicon Hip05 chip consists of varous independent system device PMU's +such as L3 cache (L3C) and Miscellaneous Nodes(MN). These PMU devices are +independent and have hardware logic to gather statistics and performance +information. + +Hip05 chip is encapsulated by multiple CPU and IO die's. The CPU die is called +as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every CPU SCCL is +further grouped as CPU clusters (CCL) which includes 4 cpu-cores each. +Each SCCL has 1 L3 cache and 1 MN units. + +The below section describes the bindings for L3C and MN PMU's + +Required Properties: + - compatible : This field contain two values. The first value is + always "hisilicon" and second value is the Module type as shown + in below examples: + (a) "hisilicon,hip05-l3c" for Hisilicon SoC L3 cache + (b) "hisilicon,hip05-mn" for Hisilicon SoC MN + +Optional Properties: + + - djtag : The registers of modules like L3 cache, MN etc. are using + the Hisilicon djtag interface. + This field contains two values. The first value is the djtag + node phandle and second value is the ID of the CPU die or SCCL. + + - interrupt-parent : A phandle indicating which interrupt controller + this PMU signals interrupts to. + + - interrupts : Interrupt lines used by this PMU. If the PMU has + multiple banks, then all IRQ lines are listed in this + property in the order of bank number. + +Example: + l3c0: l3c { + compatible = "hisilicon,hip05-l3c"; + djtag = <&djtag0 2>; /* DJTAG node for CPU die 2 + * (CPU die starts from 1) */ + interrupt-parent = <&mbigen_pc>; + interrupts = <141 4>,<142 4>, + <143 4>,<144 4>; /* IRQ lines for 4 L3 cache banks */ + }; + + mn1: mn { + compatible = "hisilicon,hip05-mn"; + djtag = <&djtag0 2>; /* DJTAG node for CPU die 2 + * (CPU die starts from 1) */ + interrupt-parent = <&mbigen_pc>; + interrupts = <146 4>; + };