| Message ID | 1470751209-31203-1-git-send-email-bharatku@xilinx.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote: > Updating device tree documentation with prefetchable memory > sapce. > Configuration space shifted to 64-bit address space. > > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> > --- > Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) Acked-by: Rob Herring <robh@kernel.org>
> Subject: Re: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation > with prefetchable memory space > > On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote: > > Updating device tree documentation with prefetchable memory sapce. > > Configuration space shifted to 64-bit address space. > > > > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> > > --- > > Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > Acked-by: Rob Herring <robh@kernel.org> Thanks Rob This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt index 337fc97..3259798 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt +++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt @@ -55,9 +55,10 @@ nwl_pcie: pcie@fd0e0000 { msi-parent = <&nwl_pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x0 0xe0000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; + ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ + 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ pcie_intc: legacy-interrupt-controller { interrupt-controller;
Updating device tree documentation with prefetchable memory sapce. Configuration space shifted to 64-bit address space. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> --- Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)