| Message ID | 1473109646-23366-1-git-send-email-jm@lentin.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Jamie, On lun., sept. 05 2016, Jamie Lentin <jm@lentin.co.uk> wrote: > This is a router based on the mv88f5181 chipset. > > http://www.netgear.com/support/product/WNR854T.aspx > http://wiki.openwrt.org/toh/netgear/wnr854t > > Signed-off-by: Jamie Lentin <jm@lentin.co.uk> > --- > This removes the contentious vendor partitioning scheme and goes back > to the original partitioning scheme used in non-DT ports to this board. > Using the same partitioning scheme should mean less surprises for > someone trying to upgrade their router. > > The non-DT PCI setup is still here, as there are other orion5x DT boards > doing very similar things, and can all be converted at the same time. I only noticed today your v2. I expected a full series actually. I am now taking care of it. I mainly have to rename most of the commit titles as they do not really match the subsystem where they will be applied. I will apply all of them on the mvebu branches to avoid to more dependency issue. However, we are very close to the end of the merge window for arm-soc. I will do my best, but the merge of the series could be delayed to 4.10. Thanks, Gregory > > The patchset in it's entirety is available at > https://github.com/lentinj/linux wnr854t-support-v2 > > Cheers, > --- > .../bindings/arm/marvell/marvell,orion5x.txt | 1 + > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 197 +++++++++++++++++++++ > arch/arm/mach-orion5x/Kconfig | 6 + > arch/arm/mach-orion5x/Makefile | 1 + > arch/arm/mach-orion5x/board-wnr854t.c | 78 ++++++++ > 6 files changed, 284 insertions(+) > create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts > create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c > > diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt > index ff3c120..748a8f2 100644 > --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt > +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt > @@ -22,3 +22,4 @@ board. Currently known boards are: > "lacie,d2-network" > "marvell,rd-88f5182-nas" > "maxtor,shared-storage-2" > +"netgear,wnr854t" > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index faacd52..4588b3c 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ > orion5x-linkstation-lswtgl.dtb \ > orion5x-lswsgl.dtb \ > orion5x-maxtor-shared-storage-2.dtb \ > + orion5x-netgear-wnr854t.dtb \ > orion5x-rd88f5182-nas.dtb > dtb-$(CONFIG_ARCH_PRIMA2) += \ > prima2-evb.dtb > diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts > new file mode 100644 > index 0000000..cce5091 > --- /dev/null > +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts > @@ -0,0 +1,197 @@ > +/* > + * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include "orion5x-mv88f5181.dtsi" > + > +/ { > + model = "Netgear WNR854-t"; > + compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", > + "marvell,orion5x"; > + > + memory { > + reg = <0x00000000 0x2000000>; /* 32 MB */ > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + soc { > + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, > + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, > + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + pinctrl-0 = <&pmx_reset_button>; > + pinctrl-names = "default"; > + > + reset { > + label = "Reset Button"; > + linux,code = <KEY_RESTART>; > + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; > + }; > + }; > + > + gpio-leds { > + compatible = "gpio-leds"; > + pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; > + pinctrl-names = "default"; > + > + led@0 { > + label = "wnr854t:green:power"; > + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; > + }; > + > + led@1 { > + label = "wnr854t:blink:power"; > + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; > + }; > + > + led@2 { > + label = "wnr854t:green:wan"; > + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; > + }; > + }; > +}; > + > +&devbus_bootcs { > + status = "okay"; > + > + devbus,keep-config; > + > + flash@0 { > + compatible = "cfi-flash"; > + reg = <0 0x800000>; > + bank-width = <2>; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + partition@0 { > + label = "kernel"; > + reg = <0x0 0x100000>; > + }; > + > + partition@100000 { > + label = "rootfs"; > + reg = <0x100000 0x660000>; > + }; > + > + partition@760000 { > + label = "uboot_env"; > + reg = <0x760000 0x20000>; > + }; > + > + partition@780000 { > + label = "uboot"; > + reg = <0x780000 0x80000>; > + read-only; > + }; > + }; > + }; > +}; > + > +&mdio { > + status = "okay"; > + > + switch: switch@0 { > + compatible = "marvell,mv88e6085"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + dsa,member = <0 0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + label = "lan3"; > + }; > + > + port@1 { > + reg = <1>; > + label = "lan4"; > + }; > + > + port@2 { > + reg = <2>; > + label = "wan"; > + }; > + > + port@3 { > + reg = <3>; > + label = "cpu"; > + }; > + > + port@5 { > + reg = <5>; > + label = "lan1"; > + }; > + > + port@7 { > + reg = <7>; > + label = "lan2"; > + }; > + }; > + }; > +}; > + > +ð { > + status = "okay"; > + > + ethernet-port@0 { > + /* Hardwired to DSA switch */ > + speed = <1000>; > + duplex = <1>; > + }; > +}; > + > +&pinctrl { > + pinctrl-0 = <&pmx_pci_gpios>; > + pinctrl-names = "default"; > + > + pmx_power_led: pmx-power-led { > + marvell,pins = "mpp0"; > + marvell,function = "gpio"; > + }; > + > + pmx_reset_button: pmx-reset-button { > + marvell,pins = "mpp1"; > + marvell,function = "gpio"; > + }; > + > + pmx_power_led_blink: pmx-power-led-blink { > + marvell,pins = "mpp2"; > + marvell,function = "gpio"; > + }; > + > + pmx_wan_led: pmx-wan-led { > + marvell,pins = "mpp3"; > + marvell,function = "gpio"; > + }; > + > + pmx_pci_gpios: pmx-pci-gpios { > + marvell,pins = "mpp4"; > + marvell,function = "gpio"; > + }; > +}; > + > +&uart0 { > + /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ > + status = "okay"; > +}; > diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig > index 89bb0fc..9acb37b 100644 > --- a/arch/arm/mach-orion5x/Kconfig > +++ b/arch/arm/mach-orion5x/Kconfig > @@ -151,6 +151,12 @@ config MACH_MSS2_DT > Say 'Y' here if you want your kernel to support the > Maxtor Shared Storage II platform. > > +config MACH_WNR854T_DT > + bool "Netgear WNR854T (Flattened Device Tree)" > + help > + Say 'Y' here if you want your kernel to support the > + Netgear WNR854T platform. > + > config MACH_WNR854T > bool "Netgear WNR854T" > help > diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile > index 4b2502b..9dff2d3 100644 > --- a/arch/arm/mach-orion5x/Makefile > +++ b/arch/arm/mach-orion5x/Makefile > @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o > obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o > obj-$(CONFIG_MACH_MSS2_DT) += board-mss2.o > obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o > +obj-$(CONFIG_MACH_WNR854T_DT) += board-wnr854t.o > diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c > new file mode 100644 > index 0000000..c506e33 > --- /dev/null > +++ b/arch/arm/mach-orion5x/board-wnr854t.c > @@ -0,0 +1,78 @@ > +/* > + * Netgear WNR854T PCI setup > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > +#include <linux/gpio.h> > +#include <linux/platform_device.h> > +#include <linux/pci.h> > +#include <asm/mach/pci.h> > +#include "common.h" > +#include "orion5x.h" > + > +#define WNR854T_PCI_SLOT0_OFFS 7 > +#define WNR854T_PCI_SLOT0_IRQ_PIN 4 > + > +static void __init wnr854t_pci_preinit(void) > +{ > + int pin; > + > + /* > + * Configure PCI GPIO IRQ pins > + */ > + pin = WNR854T_PCI_SLOT0_IRQ_PIN; > + if (gpio_request(pin, "PCI Int") == 0) { > + if (gpio_direction_input(pin) == 0) { > + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); > + } else { > + pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n", > + pin); > + gpio_free(pin); > + } > + } else { > + pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin); > + } > +} > + > +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot, > + u8 pin) > +{ > + int irq; > + > + /* > + * Check for devices with hard-wired IRQs. > + */ > + irq = orion5x_pci_map_irq(dev, slot, pin); > + if (irq != -1) > + return irq; > + > + /* > + * PCI IRQs are connected via GPIOs > + */ > + switch (slot - WNR854T_PCI_SLOT0_OFFS) { > + case 0: > + return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN); > + default: > + return -1; > + } > +} > + > +static struct hw_pci wnr854t_pci __initdata = { > + .nr_controllers = 2, > + .preinit = wnr854t_pci_preinit, > + .setup = orion5x_pci_sys_setup, > + .scan = orion5x_pci_sys_scan_bus, > + .map_irq = wnr854t_pci_map_irq, > +}; > + > +static int __init wnr854t_pci_init(void) > +{ > + if (of_machine_is_compatible("netgear,wnr854t")) > + pci_common_init(&wnr854t_pci); > + > + return 0; > +} > +/* NB: Use late_initcall so we can gpio_request() without being deferred */ > +late_initcall(wnr854t_pci_init); > -- > 2.8.1 >
On Thu, 8 Sep 2016, Gregory CLEMENT wrote: > Hi Jamie, > > On lun., sept. 05 2016, Jamie Lentin <jm@lentin.co.uk> wrote: > >> This is a router based on the mv88f5181 chipset. >> >> http://www.netgear.com/support/product/WNR854T.aspx >> http://wiki.openwrt.org/toh/netgear/wnr854t >> >> Signed-off-by: Jamie Lentin <jm@lentin.co.uk> >> --- >> This removes the contentious vendor partitioning scheme and goes back >> to the original partitioning scheme used in non-DT ports to this board. >> Using the same partitioning scheme should mean less surprises for >> someone trying to upgrade their router. >> >> The non-DT PCI setup is still here, as there are other orion5x DT boards >> doing very similar things, and can all be converted at the same time. > > I only noticed today your v2. I expected a full series actually. It seemed excessive to spam the entire patchset out again, of course I can if it makes your life easier. > I am > now taking care of it. I mainly have to rename most of the commit titles > as they do not really match the subsystem where they will be applied. Thanks, let me know if I can make myself useful. > I will apply all of them on the mvebu branches to avoid to more > dependency issue. However, we are very close to the end of the merge > window for arm-soc. I will do my best, but the merge of the series could > be delayed to 4.10. > > Thanks, > > Gregory > > >> >> The patchset in it's entirety is available at >> https://github.com/lentinj/linux wnr854t-support-v2 >> >> Cheers, >> --- >> .../bindings/arm/marvell/marvell,orion5x.txt | 1 + >> arch/arm/boot/dts/Makefile | 1 + >> arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 197 +++++++++++++++++++++ >> arch/arm/mach-orion5x/Kconfig | 6 + >> arch/arm/mach-orion5x/Makefile | 1 + >> arch/arm/mach-orion5x/board-wnr854t.c | 78 ++++++++ >> 6 files changed, 284 insertions(+) >> create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts >> create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c >> >> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt >> index ff3c120..748a8f2 100644 >> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt >> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt >> @@ -22,3 +22,4 @@ board. Currently known boards are: >> "lacie,d2-network" >> "marvell,rd-88f5182-nas" >> "maxtor,shared-storage-2" >> +"netgear,wnr854t" >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile >> index faacd52..4588b3c 100644 >> --- a/arch/arm/boot/dts/Makefile >> +++ b/arch/arm/boot/dts/Makefile >> @@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ >> orion5x-linkstation-lswtgl.dtb \ >> orion5x-lswsgl.dtb \ >> orion5x-maxtor-shared-storage-2.dtb \ >> + orion5x-netgear-wnr854t.dtb \ >> orion5x-rd88f5182-nas.dtb >> dtb-$(CONFIG_ARCH_PRIMA2) += \ >> prima2-evb.dtb >> diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts >> new file mode 100644 >> index 0000000..cce5091 >> --- /dev/null >> +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts >> @@ -0,0 +1,197 @@ >> +/* >> + * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +/dts-v1/; >> + >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/input/input.h> >> +#include "orion5x-mv88f5181.dtsi" >> + >> +/ { >> + model = "Netgear WNR854-t"; >> + compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", >> + "marvell,orion5x"; >> + >> + memory { >> + reg = <0x00000000 0x2000000>; /* 32 MB */ >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> + >> + soc { >> + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, >> + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, >> + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>; >> + }; >> + >> + gpio-keys { >> + compatible = "gpio-keys"; >> + pinctrl-0 = <&pmx_reset_button>; >> + pinctrl-names = "default"; >> + >> + reset { >> + label = "Reset Button"; >> + linux,code = <KEY_RESTART>; >> + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; >> + }; >> + }; >> + >> + gpio-leds { >> + compatible = "gpio-leds"; >> + pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; >> + pinctrl-names = "default"; >> + >> + led@0 { >> + label = "wnr854t:green:power"; >> + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; >> + }; >> + >> + led@1 { >> + label = "wnr854t:blink:power"; >> + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; >> + }; >> + >> + led@2 { >> + label = "wnr854t:green:wan"; >> + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; >> + }; >> + }; >> +}; >> + >> +&devbus_bootcs { >> + status = "okay"; >> + >> + devbus,keep-config; >> + >> + flash@0 { >> + compatible = "cfi-flash"; >> + reg = <0 0x800000>; >> + bank-width = <2>; >> + >> + partitions { >> + compatible = "fixed-partitions"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + partition@0 { >> + label = "kernel"; >> + reg = <0x0 0x100000>; >> + }; >> + >> + partition@100000 { >> + label = "rootfs"; >> + reg = <0x100000 0x660000>; >> + }; >> + >> + partition@760000 { >> + label = "uboot_env"; >> + reg = <0x760000 0x20000>; >> + }; >> + >> + partition@780000 { >> + label = "uboot"; >> + reg = <0x780000 0x80000>; >> + read-only; >> + }; >> + }; >> + }; >> +}; >> + >> +&mdio { >> + status = "okay"; >> + >> + switch: switch@0 { >> + compatible = "marvell,mv88e6085"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0>; >> + dsa,member = <0 0>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + label = "lan3"; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + label = "lan4"; >> + }; >> + >> + port@2 { >> + reg = <2>; >> + label = "wan"; >> + }; >> + >> + port@3 { >> + reg = <3>; >> + label = "cpu"; >> + }; >> + >> + port@5 { >> + reg = <5>; >> + label = "lan1"; >> + }; >> + >> + port@7 { >> + reg = <7>; >> + label = "lan2"; >> + }; >> + }; >> + }; >> +}; >> + >> +ð { >> + status = "okay"; >> + >> + ethernet-port@0 { >> + /* Hardwired to DSA switch */ >> + speed = <1000>; >> + duplex = <1>; >> + }; >> +}; >> + >> +&pinctrl { >> + pinctrl-0 = <&pmx_pci_gpios>; >> + pinctrl-names = "default"; >> + >> + pmx_power_led: pmx-power-led { >> + marvell,pins = "mpp0"; >> + marvell,function = "gpio"; >> + }; >> + >> + pmx_reset_button: pmx-reset-button { >> + marvell,pins = "mpp1"; >> + marvell,function = "gpio"; >> + }; >> + >> + pmx_power_led_blink: pmx-power-led-blink { >> + marvell,pins = "mpp2"; >> + marvell,function = "gpio"; >> + }; >> + >> + pmx_wan_led: pmx-wan-led { >> + marvell,pins = "mpp3"; >> + marvell,function = "gpio"; >> + }; >> + >> + pmx_pci_gpios: pmx-pci-gpios { >> + marvell,pins = "mpp4"; >> + marvell,function = "gpio"; >> + }; >> +}; >> + >> +&uart0 { >> + /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ >> + status = "okay"; >> +}; >> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig >> index 89bb0fc..9acb37b 100644 >> --- a/arch/arm/mach-orion5x/Kconfig >> +++ b/arch/arm/mach-orion5x/Kconfig >> @@ -151,6 +151,12 @@ config MACH_MSS2_DT >> Say 'Y' here if you want your kernel to support the >> Maxtor Shared Storage II platform. >> >> +config MACH_WNR854T_DT >> + bool "Netgear WNR854T (Flattened Device Tree)" >> + help >> + Say 'Y' here if you want your kernel to support the >> + Netgear WNR854T platform. >> + >> config MACH_WNR854T >> bool "Netgear WNR854T" >> help >> diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile >> index 4b2502b..9dff2d3 100644 >> --- a/arch/arm/mach-orion5x/Makefile >> +++ b/arch/arm/mach-orion5x/Makefile >> @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o >> obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o >> obj-$(CONFIG_MACH_MSS2_DT) += board-mss2.o >> obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o >> +obj-$(CONFIG_MACH_WNR854T_DT) += board-wnr854t.o >> diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c >> new file mode 100644 >> index 0000000..c506e33 >> --- /dev/null >> +++ b/arch/arm/mach-orion5x/board-wnr854t.c >> @@ -0,0 +1,78 @@ >> +/* >> + * Netgear WNR854T PCI setup >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> +#include <linux/gpio.h> >> +#include <linux/platform_device.h> >> +#include <linux/pci.h> >> +#include <asm/mach/pci.h> >> +#include "common.h" >> +#include "orion5x.h" >> + >> +#define WNR854T_PCI_SLOT0_OFFS 7 >> +#define WNR854T_PCI_SLOT0_IRQ_PIN 4 >> + >> +static void __init wnr854t_pci_preinit(void) >> +{ >> + int pin; >> + >> + /* >> + * Configure PCI GPIO IRQ pins >> + */ >> + pin = WNR854T_PCI_SLOT0_IRQ_PIN; >> + if (gpio_request(pin, "PCI Int") == 0) { >> + if (gpio_direction_input(pin) == 0) { >> + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); >> + } else { >> + pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n", >> + pin); >> + gpio_free(pin); >> + } >> + } else { >> + pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin); >> + } >> +} >> + >> +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot, >> + u8 pin) >> +{ >> + int irq; >> + >> + /* >> + * Check for devices with hard-wired IRQs. >> + */ >> + irq = orion5x_pci_map_irq(dev, slot, pin); >> + if (irq != -1) >> + return irq; >> + >> + /* >> + * PCI IRQs are connected via GPIOs >> + */ >> + switch (slot - WNR854T_PCI_SLOT0_OFFS) { >> + case 0: >> + return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN); >> + default: >> + return -1; >> + } >> +} >> + >> +static struct hw_pci wnr854t_pci __initdata = { >> + .nr_controllers = 2, >> + .preinit = wnr854t_pci_preinit, >> + .setup = orion5x_pci_sys_setup, >> + .scan = orion5x_pci_sys_scan_bus, >> + .map_irq = wnr854t_pci_map_irq, >> +}; >> + >> +static int __init wnr854t_pci_init(void) >> +{ >> + if (of_machine_is_compatible("netgear,wnr854t")) >> + pci_common_init(&wnr854t_pci); >> + >> + return 0; >> +} >> +/* NB: Use late_initcall so we can gpio_request() without being deferred */ >> +late_initcall(wnr854t_pci_init); >> -- >> 2.8.1 >> > >
On Mon, Sep 05, 2016 at 10:07:26PM +0100, Jamie Lentin wrote: > This is a router based on the mv88f5181 chipset. > > http://www.netgear.com/support/product/WNR854T.aspx > http://wiki.openwrt.org/toh/netgear/wnr854t > > Signed-off-by: Jamie Lentin <jm@lentin.co.uk> > --- > This removes the contentious vendor partitioning scheme and goes back > to the original partitioning scheme used in non-DT ports to this board. > Using the same partitioning scheme should mean less surprises for > someone trying to upgrade their router. > > The non-DT PCI setup is still here, as there are other orion5x DT boards > doing very similar things, and can all be converted at the same time. If we keep accepting this duplicated, legacy PCI setup, who is going to be motivated to clean things up. But it's ultimately up to Arnd and Olof. > The patchset in it's entirety is available at > https://github.com/lentinj/linux wnr854t-support-v2 > > Cheers, > --- > .../bindings/arm/marvell/marvell,orion5x.txt | 1 + > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 197 +++++++++++++++++++++ Acked-by: Rob Herring <robh@kernel.org> > arch/arm/mach-orion5x/Kconfig | 6 + > arch/arm/mach-orion5x/Makefile | 1 + > arch/arm/mach-orion5x/board-wnr854t.c | 78 ++++++++ > 6 files changed, 284 insertions(+) > create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts > create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
On Monday, September 12, 2016 12:06:25 PM CEST Rob Herring wrote: > On Mon, Sep 05, 2016 at 10:07:26PM +0100, Jamie Lentin wrote: > > This is a router based on the mv88f5181 chipset. > > > > http://www.netgear.com/support/product/WNR854T.aspx > > http://wiki.openwrt.org/toh/netgear/wnr854t > > > > Signed-off-by: Jamie Lentin <jm@lentin.co.uk> > > --- > > This removes the contentious vendor partitioning scheme and goes back > > to the original partitioning scheme used in non-DT ports to this board. > > Using the same partitioning scheme should mean less surprises for > > someone trying to upgrade their router. > > > > The non-DT PCI setup is still here, as there are other orion5x DT boards > > doing very similar things, and can all be converted at the same time. > > If we keep accepting this duplicated, legacy PCI setup, who is going to > be motivated to clean things up. But it's ultimately up to Arnd and > Olof. > I mentioned before that I'm feeling a bit uneasy about this too. Maybe we can instead leave out the PCI support from the new file for now and not delete the legacy board file? Arnd
On Monday, September 12, 2016 11:13:33 PM CEST Arnd Bergmann wrote: > On Monday, September 12, 2016 12:06:25 PM CEST Rob Herring wrote: > > On Mon, Sep 05, 2016 at 10:07:26PM +0100, Jamie Lentin wrote: > > > This is a router based on the mv88f5181 chipset. > > > > > > http://www.netgear.com/support/product/WNR854T.aspx > > > http://wiki.openwrt.org/toh/netgear/wnr854t > > > > > > Signed-off-by: Jamie Lentin <jm@lentin.co.uk> > > > --- > > > This removes the contentious vendor partitioning scheme and goes back > > > to the original partitioning scheme used in non-DT ports to this board. > > > Using the same partitioning scheme should mean less surprises for > > > someone trying to upgrade their router. > > > > > > The non-DT PCI setup is still here, as there are other orion5x DT boards > > > doing very similar things, and can all be converted at the same time. > > > > If we keep accepting this duplicated, legacy PCI setup, who is going to > > be motivated to clean things up. But it's ultimately up to Arnd and > > Olof. > > > > I mentioned before that I'm feeling a bit uneasy about this too. > > Maybe we can instead leave out the PCI support from the new > file for now and not delete the legacy board file? > Another idea that has worked in the past is that we ask everyone to do one piece of the puzzle. In this case that could be to convert the existing PCI support to a proper host driver in arch/arm/mach-orion5x/pci.c that is separate from the PCIe support (for which we already have a driver IIRC) and have it probed by calling pci_scan_root_bus() from a platform driver init function. The next person who wants DT suppor for an existing orion machine can then add DT support to that driver. Arnd
> Maybe we can instead leave out the PCI support from the new > file for now and not delete the legacy board file? Jamie, which interrupt do you see the WiFi card using? If it is IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with than if it uses GPIO 4. Thanks Andrew
On 2016-09-12 23:03, Andrew Lunn wrote: >> Maybe we can instead leave out the PCI support from the new >> file for now and not delete the legacy board file? This seems a reasonable compromise. The PCI card the router comes with isn't supported by mwl8k mainline anyway (There's STA-only firmware that can be extracted from a windows driver and PCI IDs added, but stats reporting uses a different format), so it's not a huge loss, although many did replace the card with something Atheros-based. Unfortunately the power regulator on my spare router has stopped regulating, which will make more development tricky. But will have a look at the PCI conversion if I can get hold of another. > Jamie, which interrupt do you see the WiFi card using? If it is > IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with > than if it uses GPIO 4. Definitely uses GPIO 4. # cat /proc/interrupts CPU0 17: 165966 bridge-interrupt-ctrl 2 Edge orion_event 22: 5119 interrupt-controller 3 Edge serial 24: 0 bridge-interrupt-ctrl 3 Edge orion_wdt 25: 89504 interrupt-controller 22 Edge f1072004.mdio-bus 28: 1 f1010100.gpio 1 Edge Reset Button 31: 598 f1010100.gpio 4 Level mwl8k 59: 985 interrupt-controller 21 Edge eth0 Err: 0 # iw dev wlan0 scan > /dev/null ; cat /proc/interrupts CPU0 17: 166424 bridge-interrupt-ctrl 2 Edge orion_event 22: 5250 interrupt-controller 3 Edge serial 24: 0 bridge-interrupt-ctrl 3 Edge orion_wdt 25: 89748 interrupt-controller 22 Edge f1072004.mdio-bus 28: 1 f1010100.gpio 1 Edge Reset Button 31: 708 f1010100.gpio 4 Level mwl8k 59: 985 interrupt-controller 21 Edge eth0 Err: 0 # sleep 10 ; cat /proc/interrupts CPU0 17: 167985 bridge-interrupt-ctrl 2 Edge orion_event 22: 5349 interrupt-controller 3 Edge serial 24: 0 bridge-interrupt-ctrl 3 Edge orion_wdt 25: 90603 interrupt-controller 22 Edge f1072004.mdio-bus 28: 1 f1010100.gpio 1 Edge Reset Button 31: 708 f1010100.gpio 4 Level mwl8k 59: 995 interrupt-controller 21 Edge eth0 Err: 0 # iw dev wlan0 scan > /dev/null ; cat /proc/interrupts CPU0 17: 168270 bridge-interrupt-ctrl 2 Edge orion_event 22: 5480 interrupt-controller 3 Edge serial 24: 0 bridge-interrupt-ctrl 3 Edge orion_wdt 25: 90727 interrupt-controller 22 Edge f1072004.mdio-bus 28: 1 f1010100.gpio 1 Edge Reset Button 31: 818 f1010100.gpio 4 Level mwl8k 59: 996 interrupt-controller 21 Edge eth0 Err: 0 > > Thanks > Andrew
On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote: > On 2016-09-12 23:03, Andrew Lunn wrote: > >>Maybe we can instead leave out the PCI support from the new > >>file for now and not delete the legacy board file? > > This seems a reasonable compromise. The PCI card the router comes > with isn't supported by mwl8k mainline anyway (There's STA-only > firmware that can be extracted from a windows driver and PCI IDs > added, but stats reporting uses a different format), so it's not a > huge loss, although many did replace the card with something > Atheros-based. O.K. So dropping the PCI code gets us going forward. Have we missed the merge window? > Unfortunately the power regulator on my spare router has stopped > regulating, which will make more development tricky. The Green Light of death? > >Jamie, which interrupt do you see the WiFi card using? If it is > >IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with > >than if it uses GPIO 4. > > Definitely uses GPIO 4. O.K, that makes it more interesting. As far as i can see, no other PCIe system uses a GPIO for its interrupt. There is no core support for this, or any bus driver doing it. So there is no binding to follow. Andrew
On 2016-09-13 13:36, Andrew Lunn wrote: > On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote: >> On 2016-09-12 23:03, Andrew Lunn wrote: >> >>Maybe we can instead leave out the PCI support from the new >> >>file for now and not delete the legacy board file? >> >> This seems a reasonable compromise. The PCI card the router comes >> with isn't supported by mwl8k mainline anyway (There's STA-only >> firmware that can be extracted from a windows driver and PCI IDs >> added, but stats reporting uses a different format), so it's not a >> huge loss, although many did replace the card with something >> Atheros-based. > > O.K. So dropping the PCI code gets us going forward. Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to use arch/arm/mach-orion5x/board-dt.c until everything has been converted the favoured approach? > Have we missed the merge window? I got the impression Gregory Clement had merged them? If not a good portion of this patchset is uncontroversial generic orion5x stuff, it'd be nice to get those in even if none of the router-specific stuff doesn't make it. >> Unfortunately the power regulator on my spare router has stopped >> regulating, which will make more development tricky. > > The Green Light of death? Seems that way, the 3.3v line is only getting up to 2.8v. My routers have had their power supply sections hacked in comparison to photos I've seen on GLOD pages, so I presumed this was fixed. Apparently not. Maybe I can persuade it to be useful with 5v + 3.3v in the right places. >> >Jamie, which interrupt do you see the WiFi card using? If it is >> >IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with >> >than if it uses GPIO 4. >> >> Definitely uses GPIO 4. > > O.K, that makes it more interesting. As far as i can see, no other > PCIe system uses a GPIO for its interrupt. There is no core support > for this, or any bus driver doing it. So there is no binding to > follow. Not sure if the difference is relevant at this point but it's regular PCI, not PCIe. > > Andrew
Hi Jamie, On mar., sept. 13 2016, Jamie Lentin <jm@lentin.co.uk> wrote: > On 2016-09-13 13:36, Andrew Lunn wrote: >> On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote: >>> On 2016-09-12 23:03, Andrew Lunn wrote: >>> >>Maybe we can instead leave out the PCI support from the new >>> >>file for now and not delete the legacy board file? >>> >>> This seems a reasonable compromise. The PCI card the router comes >>> with isn't supported by mwl8k mainline anyway (There's STA-only >>> firmware that can be extracted from a windows driver and PCI IDs >>> added, but stats reporting uses a different format), so it's not a >>> huge loss, although many did replace the card with something >>> Atheros-based. >> >> O.K. So dropping the PCI code gets us going forward. > > Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to > use arch/arm/mach-orion5x/board-dt.c until everything has been > converted the favoured approach? > >> Have we missed the merge window? > > I got the impression Gregory Clement had merged them? If not a good > portion of this patchset is uncontroversial generic orion5x stuff, > it'd be nice to get those in even if none of the router-specific stuff > doesn't make it. I applied on mvebu/for-next in order to find any merge conflict. It seems ok on this side. However, I didn't make the pull request to arm-soc with these patches so I fear it is too late. Arnd would you agree to accept a new pull request? Gregory
On Tuesday, September 13, 2016 9:16:28 PM CEST Gregory CLEMENT wrote: > Hi Jamie, > > On mar., sept. 13 2016, Jamie Lentin <jm@lentin.co.uk> wrote: > > > On 2016-09-13 13:36, Andrew Lunn wrote: > >> On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote: > >>> On 2016-09-12 23:03, Andrew Lunn wrote: > >>> >>Maybe we can instead leave out the PCI support from the new > >>> >>file for now and not delete the legacy board file? > >>> > >>> This seems a reasonable compromise. The PCI card the router comes > >>> with isn't supported by mwl8k mainline anyway (There's STA-only > >>> firmware that can be extracted from a windows driver and PCI IDs > >>> added, but stats reporting uses a different format), so it's not a > >>> huge loss, although many did replace the card with something > >>> Atheros-based. > >> > >> O.K. So dropping the PCI code gets us going forward. > > > > Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to > > use arch/arm/mach-orion5x/board-dt.c until everything has been > > converted the favoured approach? > > > >> Have we missed the merge window? > > > > I got the impression Gregory Clement had merged them? If not a good > > portion of this patchset is uncontroversial generic orion5x stuff, > > it'd be nice to get those in even if none of the router-specific stuff > > doesn't make it. > > I applied on mvebu/for-next in order to find any merge conflict. It > seems ok on this side. However, I didn't make the pull request to > arm-soc with these patches so I fear it is too late. > > Arnd would you agree to accept a new pull request? Yes, please just send it. We are a bit backlogged on pull requests, but because you got all the other pull requests to us early, you can always have a couple of late changes on top that we would normally pull. Arnd
diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt index ff3c120..748a8f2 100644 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt @@ -22,3 +22,4 @@ board. Currently known boards are: "lacie,d2-network" "marvell,rd-88f5182-nas" "maxtor,shared-storage-2" +"netgear,wnr854t" diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52..4588b3c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-linkstation-lswtgl.dtb \ orion5x-lswsgl.dtb \ orion5x-maxtor-shared-storage-2.dtb \ + orion5x-netgear-wnr854t.dtb \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file mode 100644 index 0000000..cce5091 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "orion5x-mv88f5181.dtsi" + +/ { + model = "Netgear WNR854-t"; + compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", + "marvell,orion5x"; + + memory { + reg = <0x00000000 0x2000000>; /* 32 MB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_reset_button>; + pinctrl-names = "default"; + + reset { + label = "Reset Button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; + pinctrl-names = "default"; + + led@0 { + label = "wnr854t:green:power"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + led@1 { + label = "wnr854t:blink:power"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + led@2 { + label = "wnr854t:green:wan"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x800000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "rootfs"; + reg = <0x100000 0x660000>; + }; + + partition@760000 { + label = "uboot_env"; + reg = <0x760000 0x20000>; + }; + + partition@780000 { + label = "uboot"; + reg = <0x780000 0x80000>; + read-only; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + switch: switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan3"; + }; + + port@1 { + reg = <1>; + label = "lan4"; + }; + + port@2 { + reg = <2>; + label = "wan"; + }; + + port@3 { + reg = <3>; + label = "cpu"; + }; + + port@5 { + reg = <5>; + label = "lan1"; + }; + + port@7 { + reg = <7>; + label = "lan2"; + }; + }; + }; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + /* Hardwired to DSA switch */ + speed = <1000>; + duplex = <1>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_pci_gpios>; + pinctrl-names = "default"; + + pmx_power_led: pmx-power-led { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_reset_button: pmx-reset-button { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_power_led_blink: pmx-power-led-blink { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_wan_led: pmx-wan-led { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_pci_gpios: pmx-pci-gpios { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; +}; + +&uart0 { + /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ + status = "okay"; +}; diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 89bb0fc..9acb37b 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -151,6 +151,12 @@ config MACH_MSS2_DT Say 'Y' here if you want your kernel to support the Maxtor Shared Storage II platform. +config MACH_WNR854T_DT + bool "Netgear WNR854T (Flattened Device Tree)" + help + Say 'Y' here if you want your kernel to support the + Netgear WNR854T platform. + config MACH_WNR854T bool "Netgear WNR854T" help diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 4b2502b..9dff2d3 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o obj-$(CONFIG_MACH_MSS2_DT) += board-mss2.o obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o +obj-$(CONFIG_MACH_WNR854T_DT) += board-wnr854t.o diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c new file mode 100644 index 0000000..c506e33 --- /dev/null +++ b/arch/arm/mach-orion5x/board-wnr854t.c @@ -0,0 +1,78 @@ +/* + * Netgear WNR854T PCI setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <asm/mach/pci.h> +#include "common.h" +#include "orion5x.h" + +#define WNR854T_PCI_SLOT0_OFFS 7 +#define WNR854T_PCI_SLOT0_IRQ_PIN 4 + +static void __init wnr854t_pci_preinit(void) +{ + int pin; + + /* + * Configure PCI GPIO IRQ pins + */ + pin = WNR854T_PCI_SLOT0_IRQ_PIN; + if (gpio_request(pin, "PCI Int") == 0) { + if (gpio_direction_input(pin) == 0) { + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + } else { + pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n", + pin); + gpio_free(pin); + } + } else { + pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin); + } +} + +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot, + u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + /* + * PCI IRQs are connected via GPIOs + */ + switch (slot - WNR854T_PCI_SLOT0_OFFS) { + case 0: + return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN); + default: + return -1; + } +} + +static struct hw_pci wnr854t_pci __initdata = { + .nr_controllers = 2, + .preinit = wnr854t_pci_preinit, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = wnr854t_pci_map_irq, +}; + +static int __init wnr854t_pci_init(void) +{ + if (of_machine_is_compatible("netgear,wnr854t")) + pci_common_init(&wnr854t_pci); + + return 0; +} +/* NB: Use late_initcall so we can gpio_request() without being deferred */ +late_initcall(wnr854t_pci_init);
This is a router based on the mv88f5181 chipset. http://www.netgear.com/support/product/WNR854T.aspx http://wiki.openwrt.org/toh/netgear/wnr854t Signed-off-by: Jamie Lentin <jm@lentin.co.uk> --- This removes the contentious vendor partitioning scheme and goes back to the original partitioning scheme used in non-DT ports to this board. Using the same partitioning scheme should mean less surprises for someone trying to upgrade their router. The non-DT PCI setup is still here, as there are other orion5x DT boards doing very similar things, and can all be converted at the same time. The patchset in it's entirety is available at https://github.com/lentinj/linux wnr854t-support-v2 Cheers, --- .../bindings/arm/marvell/marvell,orion5x.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 197 +++++++++++++++++++++ arch/arm/mach-orion5x/Kconfig | 6 + arch/arm/mach-orion5x/Makefile | 1 + arch/arm/mach-orion5x/board-wnr854t.c | 78 ++++++++ 6 files changed, 284 insertions(+) create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c