From patchwork Wed Sep 21 08:42:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chandrasekhar L X-Patchwork-Id: 9343061 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3D5D6607D4 for ; Wed, 21 Sep 2016 08:45:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2AF262A370 for ; Wed, 21 Sep 2016 08:45:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E4392A375; Wed, 21 Sep 2016 08:45:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 013BC2A370 for ; Wed, 21 Sep 2016 08:45:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bmd7w-0007cc-CB; Wed, 21 Sep 2016 08:43:36 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bmd7s-0007aQ-F8 for linux-arm-kernel@lists.infradead.org; Wed, 21 Sep 2016 08:43:33 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 12CDA61701; Wed, 21 Sep 2016 08:43:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1474447390; bh=xZg9d08r6WWYWXdMwpMMBZj9DLERq3+jexNbfuJJRzM=; h=From:To:Cc:Subject:Date:From; b=E5kGJaj/lBA0Z+LqikDg/8MJDYa+RoZu+jQLhqcgFmkMH+q5fICa5JaqET7iz2azP Tvw9yjt4i47F/bL/53o1jr0KeXHfgIZ0uDVEOpF3ic1e4Owt3w9zqbzQZpflqOpMvP plvAUf7nQ7aig/vTZV9R4C5ugKWdKzTsMFJTMotI= Received: from lingutla-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: clingutla@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6E4C66167C; Wed, 21 Sep 2016 08:43:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1474447388; bh=xZg9d08r6WWYWXdMwpMMBZj9DLERq3+jexNbfuJJRzM=; h=From:To:Cc:Subject:Date:From; b=BvcQB6LgcW2gZHCTD5fnnC/T1cYcSBZNeSyH1p5Al4gxW7n422X+lPyYMp4stX0tF 8q02EQRNE60aGIGuJ5PJC3VEJmr7k0jTdLd3RxXp0EJn8gq3hdC2Cqep7lp0Y3XR4U Kwj3plZzXqXmHOJVHZu2nxDDAfsTrVB0BLecJbLk= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 6E4C66167C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=clingutla@codeaurora.org From: Lingutla Chandrasekhar To: andy.gross@linaro.org, marc.zyngier@arm.com, tglx@linutronix.de, jason@lakedaemon.net Subject: [RFC] irqchip/gic-v3: Implement suspend and resume callbacks Date: Wed, 21 Sep 2016 14:12:39 +0530 Message-Id: <1474447359-29551-1-git-send-email-clingutla@codeaurora.org> X-Mailer: git-send-email 2.8.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160921_014332_635270_07CFCA5E X-CRM114-Status: GOOD ( 14.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lingutla Chandrasekhar , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Implement suspend and resume syscore_ops to disable and enable non wake up capable interrupts. When system enters suspend, enable only wakeup capable interrupts. While resuming, enable previously enabled interrupts and show triggered/pending interrupts. Signed-off-by: Lingutla Chandrasekhar diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index ede5672..511a5a1 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -57,6 +58,10 @@ struct gic_chip_data { u32 nr_redist_regions; unsigned int irq_nr; struct partition_desc *ppi_descs[16]; +#ifdef CONFIG_PM + unsigned int wakeup_irqs[32]; + unsigned int enabled_irqs[32]; +#endif }; static struct gic_chip_data gic_data __read_mostly; @@ -330,6 +335,81 @@ static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) return 0; } +#ifdef CONFIG_PM +static int gic_suspend(void) +{ + unsigned int i; + void __iomem *base = gic_data.dist_base; + + for (i = 0; i * 32 < gic->irq_nr; i++) { + gic->enabled_irqs[i] + = readl_relaxed(base + GICD_ISENABLER + i * 4); + /* disable all of them */ + writel_relaxed(0xffffffff, base + GICD_ICENABLER + i * 4); + /* enable the wakeup set */ + writel_relaxed(gic->wakeup_irqs[i], + base + GICD_ISENABLER + i * 4); + } + return 0; +} + +static void gic_show_pending(void) +{ + unsigned int i; + u32 enabled; + u32 pending[32]; + void __iomem *base = gic_data.dist_base; + + for (i = 0; i * 32 < gic->irq_nr; i++) { + enabled = readl_relaxed(base + GICD_ICENABLER + i * 4); + pending[i] = readl_relaxed(base + GICD_ISPENDR + i * 4); + pending[i] &= enabled; + } + + for_each_set_bit(i, (unsigned long *)pending, gic->irq_nr) { + unsigned int irq = irq_find_mapping(gic->domain, i); + struct irq_desc *desc = irq_to_desc(irq); + const char *name = "null"; + + if (desc == NULL) + name = "stray irq"; + else if (desc->action && desc->action->name) + name = desc->action->name; + + pr_debug("Pending IRQ: %d [%s]\n", __func__, irq, name); + } +} + +static void gic_resume(void) +{ + unsigned int i; + void __iomem *base = gic_data.dist_base; + + gic_show_pending(); + + for (i = 0; i * 32 < gic->irq_nr; i++) { + /* disable all of them */ + writel_relaxed(0xffffffff, base + GICD_ICENABLER + i * 4); + /* enable the enabled set */ + writel_relaxed(gic->enabled_irqs[i], + base + GICD_ISENABLER + i * 4); + } +} + +static struct syscore_ops gic_syscore_ops = { + .suspend = gic_suspend, + .resume = gic_resume, +}; + +static int __init gic_init_sys(void) +{ + register_syscore_ops(&gic_syscore_ops); + return 0; +} +device_initcall(gic_init_sys); + +#endif + static u64 gic_mpidr_to_affinity(unsigned long mpidr) { u64 aff; @@ -666,6 +746,32 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, #define gic_smp_init() do { } while(0) #endif +#ifdef CONFIG_PM +int gic_set_wake(struct irq_data *d, unsigned int on) +{ + int ret = -ENXIO; + unsigned int reg_offset, bit_offset; + unsigned int gicirq = gic_irq(d); + struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); + + /* per-cpu interrupts cannot be wakeup interrupts */ + WARN_ON(gicirq < 32); + + reg_offset = gicirq / 32; + bit_offset = gicirq % 32; + + if (on) + gic_data->wakeup_irqs[reg_offset] |= 1 << bit_offset; + else + gic_data->wakeup_irqs[reg_offset] &= ~(1 << bit_offset); + + return ret; +} + +#else +#define gic_set_wake NULL +#endif + #ifdef CONFIG_CPU_PM /* Check whether it's single security state view */ static bool gic_dist_security_disabled(void) @@ -707,6 +813,7 @@ static struct irq_chip gic_chip = { .irq_eoi = gic_eoi_irq, .irq_set_type = gic_set_type, .irq_set_affinity = gic_set_affinity, + .irq_set_wake = gic_set_wake, .irq_get_irqchip_state = gic_irq_get_irqchip_state, .irq_set_irqchip_state = gic_irq_set_irqchip_state, .flags = IRQCHIP_SET_TYPE_MASKED, @@ -723,6 +830,7 @@ static struct irq_chip gic_eoimode1_chip = { .irq_set_irqchip_state = gic_irq_set_irqchip_state, .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, .flags = IRQCHIP_SET_TYPE_MASKED, + .irq_set_wake = gic_set_wake, }; #define GIC_ID_NR (1U << gic_data.rdists.id_bits)