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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR03MB2621 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160923_002551_582853_E1A246B4 X-CRM114-Status: GOOD ( 15.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alison.wang@nxp.com, jason.jin@nxp.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The ARMv8 architecture supports two execution state, AArch64 and AArch32. To support KVM in AArch32 execution state for ARMv8, Cortex-A53 and Cortex-A72 need to be added for target-specific checks. Signed-off-by: Alison Wang --- arch/arm/include/asm/cputype.h | 2 ++ arch/arm/kvm/guest.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 754f86f..4f8c632 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -75,6 +75,8 @@ #define ARM_CPU_PART_CORTEX_A12 0x4100c0d0 #define ARM_CPU_PART_CORTEX_A17 0x4100c0e0 #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 +#define ARM_CPU_PART_CORTEX_A53_AARCH32 0x4100d030 +#define ARM_CPU_PART_CORTEX_A72_AARCH32 0x4100d080 #define ARM_CPU_PART_MASK 0xff00fff0 /* DEC implemented cores */ diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c index 9aca920..462a099 100644 --- a/arch/arm/kvm/guest.c +++ b/arch/arm/kvm/guest.c @@ -252,6 +252,8 @@ int __attribute_const__ kvm_target_cpu(void) { switch (read_cpuid_part()) { case ARM_CPU_PART_CORTEX_A7: + case ARM_CPU_PART_CORTEX_A53_AARCH32: + case ARM_CPU_PART_CORTEX_A72_AARCH32: return KVM_ARM_TARGET_CORTEX_A7; case ARM_CPU_PART_CORTEX_A15: return KVM_ARM_TARGET_CORTEX_A15;