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ARM: dts: socfpga: enable arm,shared-override in the pl310

Message ID 1474918499-9811-1-git-send-email-dinguyen@opensource.altera.com (mailing list archive)
State New, archived
Headers show

Commit Message

dinguyen@opensource.altera.com Sept. 26, 2016, 7:34 p.m. UTC 
From: Dinh Nguyen <dinguyen@opensource.altera.com>

Enable the bit(22) shared-override bit for the SoCFPGA family. While at it,
enable the prefetch-data and prefetch-instr settings for the Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga.dtsi         |    1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi |    3 +++
 2 files changed, 4 insertions(+)
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Patch

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 9f48141..28ff6e4 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -686,6 +686,7 @@ 
 			arm,data-latency = <2 1 1>;
 			prefetch-data = <1>;
 			prefetch-instr = <1>;
+			arm,shared-override;
 		};
 
 		mmc: dwmmc0@ff704000 {
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 94000cb..16fcb9f 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -573,6 +573,9 @@ 
 			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 			cache-unified;
 			cache-level = <2>;
+			prefetch-data = <1>;
+			prefetch-instr = <1>;
+			arm,shared-override;
 		};
 
 		mmc: dwmmc0@ff808000 {