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[90.116.208.57]) by smtp.googlemail.com with ESMTPSA id 193sm1850999wmo.14.2016.10.07.01.28.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 07 Oct 2016 01:28:25 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, davem@davemloft.net, f.fainelli@gmail.com, andrew@lunn.ch Subject: [PATCH v4 03/10] ARM: sun8i: dt: Add DT bindings documentation for Allwinner sun8i-emac Date: Fri, 7 Oct 2016 10:25:50 +0200 Message-Id: <1475828757-926-4-git-send-email-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.7.3 In-Reply-To: <1475828757-926-1-git-send-email-clabbe.montjoie@gmail.com> References: <1475828757-926-1-git-send-email-clabbe.montjoie@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161007_012848_739262_2B3B1F7B X-CRM114-Status: GOOD ( 14.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: netdev@vger.kernel.org, Corentin Labbe , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds documentation for Device-Tree bindings for the Allwinner sun8i-emac driver. Signed-off-by: Corentin Labbe --- .../bindings/net/allwinner,sun8i-emac.txt | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt new file mode 100644 index 0000000..92e4ef3b --- /dev/null +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt @@ -0,0 +1,70 @@ +* Allwinner sun8i EMAC ethernet controller + +Required properties: +- compatible: should be one of the following string: + "allwinner,sun8i-a83t-emac" + "allwinner,sun8i-h3-emac" + "allwinner,sun50i-a64-emac" +- reg: address and length of the register for the device. +- syscon: A phandle to the syscon of the SoC +- interrupts: interrupt for the device +- clocks: A phandle to the reference clock for this device +- clock-names: should be "ahb" +- resets: A phandle to the reset control for this device +- reset-names: should be "ahb" +- phy-mode: See ethernet.txt +- phy-handle: See ethernet.txt +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +Optional properties: +- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07. Default is 0) +- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F. Default is 0) +Both delay properties does not have units, there are arbitrary value. +The TX/RX clock delay chain settings are board specific and could be found +in vendor FEX files. + +Optional properties for "allwinner,sun8i-h3-emac": +- allwinner,leds-active-low: EPHY LEDs are active low + +Required child node of emac: +- mdio bus node: should be named mdio + +Required properties of the mdio node: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +The device node referenced by "phy" or "phy-handle" should be a child node +of the mdio node. See phy.txt for the generic PHY bindings. + +Required properties of the phy node with "allwinner,sun8i-h3-emac": +- clocks: an extra phandle to the reference clock for the EPHY +- resets: an extra phandle to the reset control for the EPHY + +Example: + +emac: ethernet@01c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "ahb"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "ahb"; + #address-cells = <1>; + #size-cells = <0>; + + phy = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; +};