From patchwork Fri Oct 7 21:31:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tyler Baicar X-Patchwork-Id: 9367703 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8B2A860487 for ; Fri, 7 Oct 2016 21:37:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8186529845 for ; Fri, 7 Oct 2016 21:37:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 74E8C29847; Fri, 7 Oct 2016 21:37:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0EA9B2984D for ; Fri, 7 Oct 2016 21:37:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bscng-0001k3-EP; Fri, 07 Oct 2016 21:35:28 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bsclZ-0006yq-57 for linux-arm-kernel@lists.infradead.org; Fri, 07 Oct 2016 21:33:24 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 352A361AC2; Fri, 7 Oct 2016 21:32:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1475875976; bh=MbN62s0Tvpr2jkESKkTBy4AxE6g6+HyQ9DLb04zMGZg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mRbIvFqvSfoGZc/G6z3um5XLGW5LU/5b92V3IW8QBjGeSpQ4u34qXyYWX84KZEWAL 8OdYkCxHSv+wsSfWlWf1Rr6N5UFcvu3SkvAx1qkf0hyRYJZgij8UaZKaqmCQu4Ud4I AjHCorIfX2YualPnMYOCT8fpmjru+/25B+TgbRRw= Received: from tbaicar-lnx.qualcomm.com (unknown [129.46.14.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: tbaicar@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5B53261C33; Fri, 7 Oct 2016 21:32:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1475875957; bh=MbN62s0Tvpr2jkESKkTBy4AxE6g6+HyQ9DLb04zMGZg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y/GiNY8j3vnakUyaRC39KN9UkbgVJX9INX9N/WiR21RYLs/ap8x9pbIGfPAfQKSJB JqYpMPHDTk/LWnNw1VQj0Xprsj3QZNdjyKQ2rx4/zSIodFngeCoLJsZUQ8471jbR/C xtjRXhyLYIElGnttMSQLGrLOZ9URAnbIfg8DJO2Q= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 5B53261C33 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=tbaicar@codeaurora.org From: Tyler Baicar To: christoffer.dall@linaro.org, marc.zyngier@arm.com, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, rjw@rjwysocki.net, lenb@kernel.org, matt@codeblueprint.co.uk, robert.moore@intel.com, lv.zheng@intel.com, mark.rutland@arm.com, james.morse@arm.com, akpm@linux-foundation.org, sandeepa.s.prabhu@gmail.com, shijie.huang@arm.com, paul.gortmaker@windriver.com, tomasz.nowicki@linaro.org, fu.wei@linaro.org, rostedt@goodmis.org, bristot@redhat.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, Dkvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, devel@acpica.org Subject: [PATCH V3 09/10] trace, ras: add ARM processor error trace event Date: Fri, 7 Oct 2016 15:31:21 -0600 Message-Id: <1475875882-2604-10-git-send-email-tbaicar@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1475875882-2604-1-git-send-email-tbaicar@codeaurora.org> References: <1475875882-2604-1-git-send-email-tbaicar@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161007_143317_465414_2F8CF649 X-CRM114-Status: GOOD ( 12.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tyler Baicar MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently there are trace events for the various RAS errors with the exception of ARM processor type errors. Add a new trace event for such errors so that the user will know when they occur. These trace events are consistent with the ARM processor error section type defined in UEFI 2.6 spec section N.2.4.4. Signed-off-by: Tyler Baicar --- drivers/firmware/efi/cper.c | 9 ++++++ drivers/ras/ras.c | 1 + include/ras/ras_event.h | 67 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+) diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index f9ffba6..21b8a6f 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -34,6 +34,7 @@ #include #include #include +#include #define INDENT_SP " " @@ -256,6 +257,14 @@ static void cper_print_proc_armv8(const char *pfx, CPER_ARMV8_INFO_VALID_PHYSICAL_ADDR) printk("%sphysical fault address: 0x%016llx\n", newpfx, err_info->physical_fault_addr); + trace_arm_event(proc->affinity_level, proc->mpidr, proc->midr, + proc->running_state, proc->psci_state, + err_info->version, err_info->type, + err_info->multiple_error, + err_info->validation_bits, + err_info->error_info, + err_info->virt_fault_addr, + err_info->physical_fault_addr); err_info += 1; } diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c index fb2500b..8ba5a94 100644 --- a/drivers/ras/ras.c +++ b/drivers/ras/ras.c @@ -28,3 +28,4 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(extlog_mem_event); #endif EXPORT_TRACEPOINT_SYMBOL_GPL(mc_event); EXPORT_TRACEPOINT_SYMBOL_GPL(unknown_sec_event); +EXPORT_TRACEPOINT_SYMBOL_GPL(arm_event); diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index 5861b6f..eb2719a 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -162,6 +162,73 @@ TRACE_EVENT(mc_event, ); /* + * ARM Processor Events Report + * + * This event is generated when hardware detects an ARM processor error + * has occurred. UEFI 2.6 spec section N.2.4.4. + */ +TRACE_EVENT(arm_event, + + TP_PROTO(const u8 affinity, + const u64 mpidr, + const u64 midr, + const u32 running_state, + const u32 psci_state, + const u8 version, + const u8 type, + const u16 err_count, + const u8 flags, + const u64 info, + const u64 virt_fault_addr, + const u64 phys_fault_addr), + + TP_ARGS(affinity, mpidr, midr, running_state, psci_state, + version, type, err_count, flags, info, virt_fault_addr, + phys_fault_addr), + + TP_STRUCT__entry( + __field(u8, affinity) + __field(u64, mpidr) + __field(u64, midr) + __field(u32, running_state) + __field(u32, psci_state) + __field(u8, version) + __field(u8, type) + __field(u16, err_count) + __field(u8, flags) + __field(u64, info) + __field(u64, virt_fault_addr) + __field(u64, phys_fault_addr) + ), + + TP_fast_assign( + __entry->affinity = affinity; + __entry->mpidr = mpidr; + __entry->midr = midr; + __entry->running_state = running_state; + __entry->psci_state = psci_state; + __entry->version = version; + __entry->type = type; + __entry->err_count = err_count; + __entry->flags = flags; + __entry->info = info; + __entry->virt_fault_addr = virt_fault_addr; + __entry->phys_fault_addr = phys_fault_addr; + ), + + TP_printk("affinity level: %d; MPIDR: %016llx; MIDR: %016llx; " + "running state: %d; PSCI state: %d; version: %d; type: %d; " + "error count: 0x%04x; flags: 0x%02x; info: %016llx; " + "virtual fault address: %016llx; " + "physical fault address: %016llx", + __entry->affinity, __entry->mpidr, __entry->midr, + __entry->running_state, __entry->psci_state, __entry->version, + __entry->type, __entry->err_count, __entry->flags, + __entry->info, __entry->virt_fault_addr, + __entry->phys_fault_addr) +); + +/* * Unknown Section Report * * This event is generated when hardware detected a hardware